Verilog实现74LS194芯片

module reg_74LS194 (
	input wire CR_n,
  input wire CP,
  input wire S0,S1,
  input wire Dsl,Dsr,
  input wire D0,D1,D2,D3,
  output wire Q0,Q1,Q2,Q3
  
);

	reg [0:3] q_reg=4'b0000;
	wire [1:0] s_reg;
	assign s_reg={S1,S0};
	always @(posedge CP or posedge CR_n) begin 
		if (!CR_n) begin
			q_reg<=4'b0000;
		end else begin
			case (s_reg)
				2'b00 :q_reg<=q_reg;
				2'b01 :q_reg<={Dsr,q_reg[0:2]};
				2'b10 :q_reg<={q_reg[1:3],Dsl};
				2'b11 :q_reg<={D0,D1,D2,D3};
				default:q_reg<=4'b0000;
			endcase
		end
	end
	
	assign Q0=q_reg[0];
	assign Q1=q_reg[1];
	assign Q2=q_reg[2];
	assign Q3=q_reg[3];
endmodule
	

module reg_74LS194_tb ();

  reg clk;
	wire CR_n;
  reg[1:0] S;
  reg Dsl,Dsr;
  wire[3:0] D;
  wire[3:0] Q;
  
  wire [4:0] duty=2;
  wire [4:0] period=7;
  wire [4:0] duty1=3;
  wire [4:0] period1=4;
  reg [4:0] count=0;
  reg [4:0] count1=0;
  
  reg_74LS194 ut(.CR_n(CR_n),
  							 .CP(clk),
  							 .S0(S[0]),
  							 .S1(S[1]),
  							 .Dsl(Dsl),
  							 .Dsr(Dsr),
  							 .D0(D[0]),
  							 .D1(D[1]),
  							 .D2(D[2]),
  							 .D3(D[3]),
  							 .Q0(Q[0]),
  							 .Q1(Q[1]),
  							 .Q2(Q[2]),
  							 .Q3(Q[3])
  							 );
  							 
   always @(posedge clk) begin
   	if (count==period-1) begin
   		count<=0;
   	end else begin
   		count<=count+1;
   	end
  end
  
  always @(posedge clk) begin
  	if (count<duty) begin
  		Dsl<=1'b0;
  		Dsr<=1'b1;
  	end else begin
  		Dsl<=1'b1;
  		Dsr<=1'b0;
  	end
  end
  
  
 
  
  always @(posedge clk) begin
   	if (count1==period1-1) begin
   		count1<=0;
   	end else begin
   		count1<=count1+1;
   	end
  end
  
  
  always @(posedge clk) begin
  	if (count1<duty1) begin
  		S[0]<=1'b0;
  		S[1]<=1'b1;
  	end else begin
  		S[1]<=1'b0;
  		S[0]<=1'b1;
  	end
  end
  
  initial begin 
  	clk=1'b0;
  	forever #50 clk=~clk;
  end
  
  assign D=4'b1111;
  
  initial begin
    #2000 $stop;
  end
  	
  
endmodule

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