根据java代码画状态图,来自8位处理器的verilog代码的状态转换图

我正在尝试从下面的verilog代码制作状态转换图，但有一些困难 .

//Execution Unit Control Logic

模块eucl(时钟，op1，op2，op3，数据，操作码，数据输出，p_c，output_pc，en_ram，wram，str，load_ram);

输入[7：0] p_c; // PC的输入值

输入[2：0] op1，op2，op3; //操作数

输入[3：0]操作码;

output [7：0] output_pc; // PC的输出值

输入[7：0]数据;

电线[3：0]标志;

输出reg en_ram，wram，str，load_ram;

reg [7：0]分支;

reg p_c_val，check_branch;

输入时钟;

输出[7：0]数据输出;

reg ld，write，enable_alu，en_Memory;

reg [2：0] addr;

reg [2：0] control_bus;

reg [4：0] state = 5'b00000; //状态机

assign output_pc = check_branch？ branch：p_c p_c_val;

初始

开始

分支= 0;

p_c_val = 0;

check_branch = 0;

load_ram = 0;

STR = 0;

LD = 0;

写= 0;

enable_alu = 0;

en_Memory = 0;

WRAM = 0;

en_ram = 0;

结束

execution_unit EU(.ld(ld),. clock(clock),. write(write),. enable_alu(enable_alu),. en_Memory(en_Memory)， . addr(addr),. indata(data),. outdata(dataout) ，.fn_sel(control_bus),. flag_register(标志));

总是@(posedge clock)

开始

check_branch <= 0;

LD <= 0;

写<= 0;

enable_alu <= 0;

en_Memory <= 0;

p_c_val <= 0;

wram <= 0;

en_ram <= 0;

branch <= data;

load_ram <= 0;

str <= 0;

if(state == 5'b01111)//增加程序计数器的值

开始

状态<= 5'b00000; //重置为零状态

p_c_val <= 1;

结束

else if(state == 5'b11111)//分支

开始

check_branch <= 1;

州<= 5'b00000;

结束

否则if(opcode == 4'b0001)//从op1移动到op2

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1; //启用内存进行读取

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= op2;

en_Memory <= 1;

写<= 1;

州<= 5'b01111; //增加PC

结束

结束

否则if(opcode == 4'b0010)//加载到内存

开始

if(state == 5'b00000)

开始

addr <= op1;

ld <= 1; //加载内存

en_Memory <= 1;

写<= 1;

州<= 5'b01111;

结束

结束

否则如果(操作码== 4'b0011)//添加

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= 3'b000; //将op1写入R0

en_Memory <= 1;

写<= 1;

州<= 5'b00010;

结束

否则if(state == 5'b00010)

开始

addr <= op2;

en_Memory <= 1;

州<= 5'b00011;

结束

否则if(state == 5'b00011)

开始

addr <= 3'b001; //将op2写入R1

en_Memory <= 1;

写<= 1;

州<= 5'b00100;

结束

否则if(state == 5'b00100)

开始

control_bus <= 3'b000;

enable_alu <= 1;

州<= 5'b00101;

结束

否则if(state == 5'b00101)

开始

addr <= 3'b000; //读取存储在R0中的值(标准输出寄存器)

en_Memory <= 1;

州<= 5'b00110;

结束

否则如果(州== 5'b00110)

开始

addr <= op3; //将R0的值写入op3

en_Memory <= 1;

写<= 1;

州<= 5'b01111;

结束

结束

否则if(opcode == 4'b0100)//减去

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= 3'b000;

en_Memory <= 1;

写<= 1;

州<= 5'b00010;

结束

否则if(state == 5'b00010)

开始

addr <= op2;

en_Memory <= 1;

州<= 5'b00011;

结束

否则if(state == 5'b00011)

开始

addr <= 3'b001;

en_Memory <= 1;

写<= 1;

州<= 5'b00100;

结束

否则if(state == 5'b00100)

开始

control_bus <= 3'b001;

enable_alu <= 1;

州<= 5'b00101;

结束

否则if(state == 5'b00101)

开始

addr <= 3'b000;

en_Memory <= 1;

州<= 5'b00110;

结束

否则如果(州== 5'b00110)

开始

addr <= op3;

en_Memory <= 1;

写<= 1;

州<= 5'b01111;

结束

结束

否则如果(操作码== 4'b0101)//和

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= 3'b000;

en_Memory <= 1;

写<= 1;

州<= 5'b00010;

结束

否则if(state == 5'b00010)

开始

addr <= op2;

en_Memory <= 1;

州<= 5'b00011;

结束

否则if(state == 5'b00011)

开始

addr <= 3'b001;

en_Memory <= 1;

写<= 1;

州<= 5'b00100;

结束

否则if(state == 5'b00100)

开始

control_bus <= 3'b010;

enable_alu <= 1;

州<= 5'b00101;

结束

否则if(state == 5'b00101)

开始

addr <= 3'b000;

en_Memory <= 1;

州<= 5'b00110;

结束

否则如果(州== 5'b00110)

开始

addr <= op3;

en_Memory <= 1;

写<= 1;

州<= 5'b01111;

结束

结束

否则如果(操作码== 4'b0110)//或

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= 3'b000;

en_Memory <= 1;

写<= 1;

州<=5'b00010;

结束

否则if(state == 5'b00010)

开始

addr <= op2;

en_Memory <= 1;

州<= 5'b00011;

结束

否则if(state == 5'b00011)

开始

addr <= 3'b001;

en_Memory <= 1;

写<= 1;

州<= 5'b00100;

结束

否则if(state == 5'b00100)

开始

control_bus <= 3'b011;

enable_alu <= 1;

州<= 5'b00101;

结束

否则if(state == 5'b00101)

开始

addr <= 3'b000;

en_Memory <= 1;

州<= 5'b00110;

结束

否则如果(州== 5'b00110)

开始

addr <= op3;

en_Memory <= 1;

写<= 1;

州<= 5'b01111;

结束

结束

否则如果(操作码== 4'b0111)//左移

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= 3'b000;

en_Memory <= 1;

写<= 1;

州<= 5'b00010;

结束

否则if(state == 5'b00010)

开始

control_bus <= 3'b100;

enable_alu <= 1;

州<= 5'b00011;

结束

否则if(state == 5'b00011)

开始

addr <= 3'b000;

en_Memory <= 1;

州<= 5'b00100;

结束

否则if(state == 5'b00100)

开始

addr <= op1;

en_Memory <= 1;

写<= 1;

州<= 5'b01111;

结束

结束

否则如果(操作码== 4'b1000)//右移

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= 3'b000;

en_Memory <= 1;

写<= 1;

州<= 5'b00010;

结束

否则if(state == 5'b00010)

开始

control_bus <= 3'b101;

enable_alu <= 1;

州<= 5'b00011;

结束

否则if(state == 5'b00011)

开始

addr <= 3'b000;

en_Memory <= 1;

州<= 5'b00100;

结束

否则if(state == 5'b00100)

开始

addr <= op1;

en_Memory <= 1;

写<= 1;

州<= 5'b01111;

结束

结束

else if(opcode == 4'b1001)//从内存中存储到RAM中

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

en_ram <= 1;

wram <= 1;

str <= 1; // DATA_OUT

州<= 5'b01111;

结束

结束

否则if(opcode == 4'b1010)//比较标志如果op1> op2

开始

if(state == 5'b00000)

开始

addr <= op1;

en_Memory <= 1;

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

addr <= 3'b000;

en_Memory <= 1;

写<= 1;

州<= 5'b00010;

结束

否则if(state == 5'b00010)

开始

addr <= op2;

en_Memory <= 1;

州<= 5'b00011;

结束

否则if(state == 5'b00011)

开始

addr <= 3'b001;

en_Memory <= 1;

写<= 1;

州<= 5'b00100;

结束

否则if(state == 5'b00100)

开始

control_bus <= 3'b110;

enable_alu <= 1;

州<= 5'b01111;

结束

结束

else if(opcode == 4'b1011)//如果更大则分支

开始

if(state == 5'b00000)

开始

if(flag [1])

州<= 5'b11111; //科

其他

州<= 5'b01111; //不要分支

结束

结束

否则if(opcode == 4'b1100)//如果为零则分支

开始

if(state == 5'b00000)

开始

if(flag [0])

州<= 5'b11111;

其他

州<= 5'b01111;

结束

结束

否则if(操作码== 4'b1101)//分支如果移出位

开始

if(state == 5'b00000)

开始

if(flag [2])

州<= 5'b11111;

其他

州<= 5'b01111;

结束

结束

否则if(opcode == 4'b1110)//从RAM加载到内存

开始

if(state == 5'b00000)

开始

en_ram <= 1;

load_ram <= 1; //从RAM读取

州<= 5'b00001;

结束

否则if(state == 5'b00001)

开始

load_ram <= 1;

addr <= op1;

ld <= 1;

en_Memory <= 1;

写<= 1; //写入内存

州<= 5'b01111;

结束

结束

else if(opcode == 4'b1111)//立即加载到RAM

开始

en_ram <= 1;

wram <= 1;

州<= 5'b01111;

结束

结束

endmodule