HDLBits 之Count clock

这题目可以将hh,mm和ss 分开写，易于操作。

这题目使用16进制，我们人为的逢10进1，每一位占用4个Bits。这题目用10进制也可以。

此外，Pm仅仅在11h59m59s时候翻转，重置时为12h00m00s,  12h59m59s时变成1h00m00s.这点是题目比较怪的地方，与我们日常认知的时钟有一定区别。

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    always @(posedge clk) begin
        if (reset)
            ss<=8'h0;
        else if (ena) begin
            if (ss==8'h59)
                ss<=8'h00;
            else if (ss[3:0]==4'h9) begin
                ss[7:4]<=ss[7:4]+1'h1;
                ss[3:0]<=4'h0;
            end
            else  begin
                ss[7:4]<=ss[7:4];
                ss[3:0]<=ss[3:0]+1'h1;
            end
        end
        else
            ss<=ss;
    end
    
    always @(posedge clk) begin
         if (reset)
            mm<=8'h0;
        else if (ena && ss==8'h59) begin 
            if (mm==8'h59)
                mm<=8'h00;
            else if (mm[3:0]==4'h9) begin
                mm[7:4]<=mm[7:4]+1'h1;
                mm[3:0]<=4'h0;
            end
            else  begin
                mm[7:4]<=mm[7:4];
                mm[3:0]<=mm[3:0]+1'h1;
            end
        end
        else
            mm<=mm;
    end
    
    always @(posedge clk) begin
         if (reset)
            hh<=8'h12;
        else if (ena && mm==8'h59 && ss ==8'h59) begin
            if (hh==8'h12)
                hh<=8'h01;
            else if (hh[3:0]==4'h9) begin
                hh[7:4]<=hh[7:4]+1'h1;
                hh[3:0]<=4'h0;
            end
            else  begin
                hh[7:4]<=hh[7:4];
                hh[3:0]<=hh[3:0]+1'h1;
            end
        end
        else
            hh<=hh;
    end 
    
    always @(posedge clk) begin
        if (reset)
        pm<=0;
        else if (ena && hh==8'h11 && mm==8'h59 && ss ==8'h59)
        pm<=!pm;
        else
        pm<=pm;
    end
  
endmodule

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