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HDLBits学习笔记（107~115)
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题目107 Shift4
题干：Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.
areset: Resets shift register to zero.
load: Loads shift register with data[3:0] instead of shifting.
ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
q: The contents of the shift register.
If both the load and ena inputs are asserted (1), the load input has higher priority.
题目大意：构建4位移位寄存器(右移位)，具有异步复位、同步加载和使能功能。AReset：将移位寄存器重置为零。load：用数据[3：0]加载移位寄存器，而不是移位。ENA：右移(Q[3]变为零，Q[0]移出并消失)。
答案：
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always@(posedge clk or posedge areset )begin
if(areset)
q<=4'b0;
else if(load)
q<=data;
else if(ena)
q<={1'b0,q[3],q[2],q[1]};
else
q<=q;
end
endmodule
题目108 Rotate100
题干：Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.
load: Loads shift register with data[99:0] instead of rotating.
ena[1:0]: Chooses whether and which direction to rotate.
2’b01 rotates right by one bit
2’b10 rotates left by one bit
2’b00 and 2’b11 do not rotate.
q: The contents of the rotator.
题目大意：构建一个可以左右旋转的寄存器，旋转器从寄存器的另一端移入移出的位，这与移位寄存器不同。
答案：
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always@(posedge clk)begin
if(load)
q<=data;
else if(ena == 2'b01)
q<={q[0],q[99:1]};
else if(ena == 2'b10)
q<={q[98:0],q[99]};
else
q<=q;
end
endmodule
题目109 Rotate100
题干：Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.
There is no difference between logical and arithmetic left shifts.
load: Loads shift register with data[63:0] instead of shifting.
ena: Chooses whether to shift.
amount: Chooses which direction and how much to shift.
2’b00: shift left by 1 bit.
2’b01: shift left by 8 bits.
2’b10: shift right by 1 bit.
2’b11: shift right by 8 bits.
q: The contents of the shifter.
题目大意：构建64位算术移位寄存器，同步加载。移位器可以向左和向右移位，并且可以按量选择移位1位或8位。
加载：用数据[63：0]加载移位寄存器，而不是移位。
ENA：选择是否移动。
数量：选择要移动的方向和移动量。
2‘b00：左移1位。
2‘B01：左移8位。
2‘b10：右移1位。
2‘b11：右移8位。
答案：
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always@(posedge clk)begin
if(load)
q<=data;
else if(ena)begin
case(amount)
2'b00:begin
q <= {q[62:0], 1'b0};
end
2'b01:begin
q <= {q[55:0], 8'b0};
end
2'b10:begin
q <= {q[63], q[63:1]};
end
2'b11:begin
q <= {{8{q[63]}}, q[63-:56]};
//从第63位依此减56次的逐个
//算术右移是用符号位填充和q的高56位
end
endcase
end
end
endmodule
题目110 Lfsr5
题干：A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a “tap” are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be “maximum-length”. A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).
The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.
题目大意：把下图用代码实现
答案：
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @ (posedge clk)
begin
if(reset)
q <= 5'b00001;
else
begin
q[4] <= 1'b0 ^ q[0];
q[3] <= q[4];
q[2] <= q[3] ^ q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
题目111 Lfsr5
题目大意：实现电路图中的时序电路
答案：
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
wire clk ;
wire L ;
wire [2:0] d ;
assign clk = KEY[0] ;
assign L = KEY[1] ;
assign d = (L)?(SW):({LEDR[2]^LEDR[1], LEDR[0], LEDR[2]});
always @(posedge clk ) begin
LEDR <= d;
end
endmodule
题目112 Lfsr32
题干：Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.
题目大意：线性位移寄存器的第32，22，2，1前有异或门；
答案：
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
wire [31:0] d ;
assign d = {q[0]^1'b0, q[31:23], q[22]^q[0] ,q[21:3], q[2]^q[0], q[1]^q[0]} ;
always @(posedge clk ) begin
if(reset)begin
q <= 32'h1;
end
else begin
q <= d;
end
end
endmodule
题目113 Exams/m2014 q4k
题干：Implement the following circuit:
题目分析：注意resetn!!
答案：
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
wire [3:0] d ;
reg [3:0] q ;
assign d = {in, q[3:1]};
assign out = q[0];
always @(posedge clk ) begin
if(!resetn)begin
q <= 4'b0;
end
else begin
q <= d;
end
end
endmodule
题目114 Exams/m2014 q4k
题干：Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.
题目大意：实现图示电路,令n等于4。
答案：
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
generate
genvar i;
for(i = 0; i<3; i++)begin:a
MUXDFF (
.w(LEDR[i+1]) ,
.e(KEY[1]) ,
.r(SW[i]) ,
.l(KEY[2]) ,
.clk(KEY[0]) ,
.q(LEDR[i])
);
end
endgenerate
MUXDFF instance1 (
.w(KEY[3]) ,
.e(KEY[1]) ,
.r(SW[3]) ,
.l(KEY[2]) ,
.clk(KEY[0]) ,
.q(LEDR[3])
);
endmodule
module MUXDFF (
input wire w ,
input wire e ,
input wire r ,
input wire l ,
input wire clk ,
output reg q
);
wire d1, d2, d;
assign d1 = (e)?(w):(q);
assign d2 = (l)?(r):(d1);
assign d = d2;
always @(posedge clk ) begin
q <= d;
end
endmodule
题目115 Exams/ece241 2013 q12
题干：In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is “random access”, as in a typical RAM. You will then use the circuit to realize a 3-input logic function.
First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]…Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit’s behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).
题目大意：在这个问题中，您将为8x1存储器设计一个电路，其中写入存储器是通过移入位来完成的，而读取是“随机存取”，就像在典型的RAM中一样。然后，您将使用该电路实现3输入逻辑功能。
首先，用8个型触发器创建一个8位移位寄存器。标记来自Q[0]…Q[7]的触发器输出。移位寄存器输入应称为S，它传入Q[0]的。enable输入控制是否转移。
然后，扩展电路，使其具有3个额外的输入A、B、C和一个输出Z。电路的行为如下：当ABC为000时，Z=Q[0]；当ABC为001时，Z=Q[1]，依此类推。您的电路应该只包含8位移位寄存器和多路复用器。(旁白：此电路称为3输入查找表(LUT))。
答案：
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] s_reg;
always @(posedge clk ) begin
if(enable)begin
s_reg <= {s_reg[6:0], S};
end
end
always@(*)begin
case({A,B,C})
3'd0:Z<=s_reg[0];
3'd1:Z<=s_reg[1];
3'd2:Z<=s_reg[2];
3'd3:Z<=s_reg[3];
3'd4:Z<=s_reg[4];
3'd5:Z<=s_reg[5];
3'd6:Z<=s_reg[6];
3'd7:Z<=s_reg[7];
default:Z<=1'b0;
endcase
end
endmodule
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