1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
`timescale 1ns / 1ps
//
// Company: 追逐者——桥的小作坊
// Engineer: 
// 
// Create Date: 2022/04/25 09:23:40
// Design Name: D触发器实现按键控制LED
// Module Name: counter4
// Project Name: 
// Target Devices: 
// Tool Versions: Vivado 2018_3
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:视频学习代码
// 
//

module flip_flop(
    input wire sys_clk, sys_ret_n, key_in,
    output reg led_out
    );
    
    always@(posedge sys_clk)
        if(sys_ret_n == 1'b0)
            led_out <= 1'b0;
        else
            led_out <= key_in;    
endmodule

1
2
3
4
5
6
7
8
9
10
11
module flip_flop(
    input wire sys_clk, sys_ret_n, key_in,
    output reg led_out
    );
    
    always@(posedge sys_clk or negedge sys_ret_n)    //添加条件
        if(sys_ret_n == 1'b0)
            led_out <= 1'b0;
        else
            led_out <= key_in;    
endmodule

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
`timescale 1ns / 1ns
//
// Company: 追逐者——桥的小作坊
// Engineer: 
// 
// Create Date: 2022/04/25 09:23:40
// Design Name: D触发器实现按键控制LED
// Module Name: counter4
// Project Name: 
// Target Devices: 
// Tool Versions: Vivado 2018_3
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:视频学习代码
// 
//
module tb_flip_flop();
    reg sys_clk, sys_ret_n, key_in;
    wire led_out;
    initial begin
        sys_clk = 1'b1;
        sys_ret_n <= 1'b0;
        key_in <= 1'b0;
        #20
        sys_ret_n <= 1'b1;
        
        #210
        sys_ret_n <= 1'b0;
        
        #40
        sys_ret_n <= 1'b1;
    end
    always #10 sys_clk = ~sys_clk;  //模拟时钟，没10ns电平翻转一次，周期20ns，频率50MHz
    always #20 key_in <= {$random} % 2;
    initial begin
        $timeformat(-9, 0, "ns", 6);
        $monitor("@time %t:key_in=%b, led_out=%b", $time, key_in, led_out);
    end
    flip_flop ff_inst(sys_clk, sys_ret_n, key_in, led_out);
endmodule