1. 可重叠和不可重叠区分

• 可重叠的序列检测器检测到一个目标串后可以不用回到初始状态，该目标串的元素的可作为下一个目标串的子串继续进行判断。
  0 1 1 0 1 0 1 0 1 1 1 0
• 不可重叠的序列检测器一次检测完成后必须回到初始状态。
  0 1 1 0 1 0 1 0 1 1 1 0

2. 可重叠序列检测器实现

2.1. 米利机

• 输出由当前状态和输入共同决定

module	mealy_overlap	(
	output		reg		dout,
	
	input		wire	clk,
	input		wire	rst,
	input		wire	din
);

	reg	[1:0]	curr_state;
	reg	[1:0]	next_state;
	
	parameter	IDLE	=	2'b 00;
	parameter	S1		=	2'b 01;
	parameter	S2		=	2'b 10;
	
	always @ (posedge clk or negedge rst)	begin
		if (!rst)	begin
			curr_state	<=	IDLE;
		end else	begin
			curr_state	<=	next_state;
		end
	end
	
	always @ (*)	begin
		case	(curr_state)
			IDLE:	begin
				if (din == 1)	begin		next_state <= S1;	dout <= 0;	end
				else			begin		next_state <= IDLE;	dout <= 0;	end
			end
			S1:		begin
				if (din == 0)	begin		next_state <= S2;	dout <= 0;	end
				else			begin		next_state <= S1;	dout <= 0;	end
			end
			S2:		begin
				if (din == 1)	begin		next_state <= S1;	dout <= 1;	end
				else			begin		next_state <= IDLE;	dout <= 0;	end
			end
			default:	begin				next_state <= IDLE;	dout <= 0;	end
		endcase
	end
	
endmodule

2.2. 摩尔机

• 输出由当前状态决定

module	moore_overlap	(
	output	reg		dout,
	
	input	wire	clk,
	input	wire	rst,
	input	wire	din
);

	reg	[1:0]	curr_state;
	reg	[1:0]	next_state;
	
	parameter	IDLE	=	2'b 00;
	parameter	S1		=	2'b 01;
	parameter	S2		=	2'b 10;
	parameter	S3		=	2'b 11;
	
	always@ (posedge clk or negedge rst)	begin
		if (!rst)	begin
			curr_state	<=	IDLE;
		end	else	begin
			curr_state	<=	next_state;
		end
	end
	
	always @ (*)	begin
		case	(curr_state)
			IDLE:	begin
				if (din == 1)		next_state	<=	S1;
				else				next_state	<=	IDLE;
			end
			S1:		begin
				if (din == 0)		next_state	<=	S2;
				else				next_state	<=	S1;
			end
			S2:		begin
				if (din == 1)		next_state	<=	S3;
				else				next_state	<=	IDLE;
			end
			S3:		begin
				if (din == 1)		next_state	<=	S1;
				else				next_state	<=	S2;
			end
			default:	begin		next_state	<=	IDLE;
			end
		endcase
	end
	
	always @ (*)	begin
		if (curr_state == S3)		dout	<=	1;
		else						dout	<=	0;
	end
	
endmodule

3. 不可重叠序列检测器实现

3.1. 米利机

module	mealy_not_overlap	(
	output		reg		dout,
	
	input		wire	clk,
	input		wire	rst,
	input		wire	din
);

	reg	[1:0]	curr_state;
	reg	[1:0]	next_state;
	
	parameter	IDLE	=	2'b 00;
	parameter	S1		=	2'b 01;
	parameter	S2		=	2'b 10;
	
	always @ (posedge clk or negedge rst)	begin
		if (!rst)	begin
			curr_state	<=	IDLE;
		end else	begin
			curr_state	<=	next_state;
		end
	end
	
	always @ (*)	begin
		case	(curr_state)
			IDLE:	begin
				if (din == 1)	begin		next_state <= S1;		dout <= 0;	end
				else			begin		next_state <= IDLE;		dout <= 0;	end
			end
			S1:		begin
				if (din == 0)	begin		next_state <= S2;		dout <= 0;	end
				else			begin		next_state <= S1;		dout <= 0;	end
			end
			S2:		begin
				if (din == 1)	begin		next_state <= IDLE;		dout <= 1;	end
				else			begin		next_state <= IDLE;		dout <= 0;	end
			end
			default:	begin				next_state <= IDLE;		dout <= 0;	end
		endcase
	end
	
endmodule

3.2. 摩尔机

module	moore_not_overlap	(
	output	reg		dout,
	
	input	wire	clk,
	input	wire	rst,
	input	wire	din
);

	reg	[1:0]	curr_state;
	reg	[1:0]	next_state;
	
	parameter	IDLE	=	2'b 00;
	parameter	S1		=	2'b 01;
	parameter	S2		=	2'b 10;
	parameter	S3		=	2'b 11;
	
	always@ (posedge clk or negedge rst)	begin
		if (!rst)	begin
			curr_state	<=	IDLE;
		end	else	begin
			curr_state	<=	next_state;
		end
	end
	
	always @ (*)	begin
		case	(curr_state)
			IDLE:	begin
				if (din == 1)		next_state	<=	S1;
				else				next_state	<=	IDLE;
			end
			S1:		begin
				if (din == 0)		next_state	<=	S2;
				else				next_state	<=	S1;
			end
			S2:		begin
				if (din == 1)		next_state	<=	S3;
				else				next_state	<=	IDLE;
			end
			S3:		begin
				if (din == 1)		next_state	<=	S1;
				else				next_state	<=	IDLE;
			end
			default:	begin		next_state	<=	IDLE;
			end
		endcase
	end
	
	always @ (*)	begin
		if (curr_state == S3)		dout	<=	1;
		else						dout	<=	0;
	end
	
endmodule

摩尔机和米利机的区别

Moore状态机的输出仅依赖于当前状态而与输入无关。想要输出dout = 1，状态S3必须形成。

Mealy状态机的输出与当前状态和输入有关。想要输出dout = 1，状态S2下输入din = 1就可以了，不需要状态S3。根据波形可对比反应更快。

最后

以上就是美丽钻石为你收集整理的Verilog 实现101序列检测器——Moore和Mealy型状态机实现可重叠和不可重叠1. 可重叠和不可重叠区分2. 可重叠序列检测器实现3. 不可重叠序列检测器实现摩尔机和米利机的区别的全部内容，希望文章能够帮你解决Verilog 实现101序列检测器——Moore和Mealy型状态机实现可重叠和不可重叠1. 可重叠和不可重叠区分2. 可重叠序列检测器实现3. 不可重叠序列检测器实现摩尔机和米利机的区别所遇到的程序开发问题。

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