计算机组成原理实验4：寄存器堆

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我是靠谱客的博主健康鞋垫，最近开发中收集的这篇文章主要介绍计算机组成原理实验4：寄存器堆，觉得挺不错的，现在分享给大家，希望可以做个参考。

概述

寄存器堆

module Register(
	input [4:0] R_Addr_A,
	input [4:0] R_Addr_B,
	input [4:0] W_Addr,
	input Write_Reg,
	input [31:0] Write_Data,
	input clk,
	input reset,
	output [31:0] R_Data_A,
	output [31:0] R_Data_B
    );
	
	reg [31:0] REG [0:31];
	
	//Write
	integer i = 0;
	always@(posedge clk,negedge reset) 
	begin
		if(!reset)
			while(i<=31) begin
				REG[i] <= 0;
				i = i+1;
			end
		else
			if(Write_Reg)
				REG[W_Addr] <= Write_Data;
	end
	//Read
	assign R_Data_A = REG[R_Addr_A];
	assign R_Data_B = REG[R_Addr_B];
	
endmodule

寄存器堆测试文件

module test;

	// Inputs
	reg [4:0] R_Addr_A;
	reg [4:0] R_Addr_B;
	reg [4:0] W_Addr;
	reg Write_Reg;
	reg [31:0] Write_Data;
	reg clk;
	reg reset;

	// Outputs
	wire [31:0] R_Data_A;
	wire [31:0] R_Data_B;

	// Instantiate the Unit Under Test (UUT)
	Register uut (
		.R_Addr_A(R_Addr_A), 
		.R_Addr_B(R_Addr_B), 
		.W_Addr(W_Addr), 
		.Write_Reg(Write_Reg), 
		.Write_Data(Write_Data), 
		.clk(clk), 
		.reset(reset), 
		.R_Data_A(R_Data_A), 
		.R_Data_B(R_Data_B)
	);
	always #25 clk=~clk;
	initial begin
		//初始化设置REG[0]的位置存放0
		R_Addr_A = 0;
		R_Addr_B = 0;
		W_Addr = 0;
		Write_Reg = 1;
		Write_Data = 0;
		clk = 0;
		reset = 1;
		
		//首先为registor写入数据
		#100 Write_Reg = 1;W_Addr = 0;Write_Data = 799;
		#100 Write_Reg = 1;W_Addr = 1;Write_Data = 54567445;
		#100 Write_Reg = 1;W_Addr = 2;Write_Data = 785656;
		#100 Write_Reg = 1;W_Addr = 3;Write_Data = 123444;
		#100 Write_Reg = 1;W_Addr = 4;Write_Data = 75644;
		#100 Write_Reg = 1;W_Addr = 5;Write_Data = 6998;
		
		//随后使用双地址进行读出操作，此时应该过去了6个时延
		#100 R_Addr_A = 0;R_Addr_B = 1;Write_Reg = 0;
		#100 R_Addr_A = 2;R_Addr_B = 3;
		#100 R_Addr_A = 4;R_Addr_B = 5;
		
		//进行复位操作
		#100 reset = 0;
		
		//检测复位后的效果
		#100 R_Addr_A = 0;R_Addr_B = 1;
		#100 R_Addr_A = 2;R_Addr_B = 3;
		#100 R_Addr_A = 4;R_Addr_B = 5;

		

	end
      
endmodule

寄存器堆和ALU连接

module Top(
	input [4:0] R_Addr_A,R_Addr_B,W_Addr,
	input Write_Reg,clk,reset,
	input [2:0] ALU_OP,
	output [31:0] ALU_F,
	output [31:0] R_Data_A,R_Data_B,
	output ZF,OF
	);
	
	Registor uu1(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,ALU_F,clk,reset,R_Data_A,R_Data_B);
	ALU uu2(ALU_OP,R_Data_A,R_Data_B,ALU_F,ZF,OF);
endmodule


module Registor(
	input [4:0] R_Addr_A,
	input [4:0] R_Addr_B,
	input [4:0] W_Addr,
	input Write_Reg,
	input [31:0] Write_Data,
	input clk,
	input reset,
	output [31:0] R_Data_A,
	output [31:0] R_Data_B
    );
	
	reg [31:0] REG [0:31];
	
	//Write
	integer i;
	initial REG[0]<=32'hF0F0F0F0;
	initial REG[1]<=32'h00000004;
   initial
		for(i=2;i<32;i=i+1) REG[i]<=0;
	always@(posedge clk,negedge reset) 
	begin
		if(!reset)
			for(i=0;i<32;i=i+1)
				REG[i] <= 0;
		else
			if(Write_Reg)
				REG[W_Addr] <= Write_Data;
	end
	//Read
	assign R_Data_A = REG[R_Addr_A];
	assign R_Data_B = REG[R_Addr_B];
	
endmodule

module ALU(
	input [2:0] ALU_OP,
	input [31:0] A,B,
	output [31:0] F,
	output ZF,OF
	);
	reg [31:0] F;
   reg C,ZF,OF;
	always@(*)begin
		C=0;OF=0;
		case(ALU_OP)
		 	3'b000:begin F=A&B; end
		 	3'b001:begin F=A|B; end
		 	3'b010:begin F=A^B; end
		 	3'b011:begin F=~(A|B); end 
		 	3'b100:begin {C,F}=A+B;OF = A[31]^B[31]^F[31]^C; end 
		 	3'b101:begin {C,F}=A-B;OF = A[31]^B[31]^F[31]^C; end 
		 	3'b110:begin F=A<B; end
		 	3'b111:begin F=B<<A; end
		endcase
		ZF = ~|F;
	end
endmodule

测试文件

module test;

	// Inputs
	reg [4:0] R_Addr_A;
	reg [4:0] R_Addr_B;
	reg [4:0] W_Addr;
	reg Write_Reg;
	reg clk;
	reg reset;
	reg [2:0] ALU_OP;

	// Outputs
	wire [31:0] ALU_F;
	wire [31:0] R_Data_A;
	wire [31:0] R_Data_B;
	wire ZF;
	wire OF;

	// Instantiate the Unit Under Test (UUT)
	Top uut (
		.R_Addr_A(R_Addr_A), 
		.R_Addr_B(R_Addr_B), 
		.W_Addr(W_Addr), 
		.Write_Reg(Write_Reg), 
		.clk(clk), 
		.reset(reset), 
		.ALU_OP(ALU_OP), 
		.ALU_F(ALU_F), 
		.R_Data_A(R_Data_A), 
		.R_Data_B(R_Data_B), 
		.ZF(ZF), 
		.OF(OF)
	);
	always #25 clk=~clk;
	initial begin
		clk = 0;
		reset = 1;
		Write_Reg = 1;
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 10;
		ALU_OP = 3'b000;
		#100;
		
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 11;
		ALU_OP = 3'b001;
		#100;
		
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 12;
		ALU_OP = 3'b010;
		#100;
		
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 13;
		ALU_OP = 3'b011;
		#100;
		
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 14;
		ALU_OP = 3'b100;
		#100;
		
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 15;
		ALU_OP = 3'b101;
		#100;
		
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 16;
		ALU_OP = 3'b110;
		#100;
		
		R_Addr_A = 0;
		R_Addr_B = 1;
		W_Addr = 17;
		ALU_OP = 3'b111;
		#100;
		
		//然后分别读出10~17号的数据
		Write_Reg = 0;
		R_Addr_A = 10;
		R_Addr_B = 11;
		#100;
		
		R_Addr_A = 12;
		R_Addr_B = 13;
		#100;
		
		R_Addr_A = 14;
		R_Addr_B = 15;
		#100;
		
		R_Addr_A = 16;
		R_Addr_B = 17;
		#100;
		
		reset = 0;
		#100;
	end
endmodule