VHDL四人抢答器

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我是靠谱客的博主隐形月饼，最近开发中收集的这篇文章主要介绍VHDL四人抢答器，觉得挺不错的，现在分享给大家，希望可以做个参考。

概述

一设计任务及要求：
（1）设计用于竞赛抢答的四人抢答器；
◇有多路抢答，抢答台数为4；
◇具有抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，并报警；
◇能显示超前抢答台号并显示犯规警报；
（2）系统复位后进入抢答状态，当有一路抢答按键按下，该路抢答信号将其余各路抢答信号封锁，同时铃声想起，直至该路按键松开，显示牌显示该路抢答台号；
（3）用VHDL语言设计符合上述功能要求的四人抢答器，并用层次化设计方法设计该电路；
二采用自顶向下模式，总体布局直至分化模块，由模块组成整体。
2 模块功能分析
2.1编码器
编码器的作用是将开关信息转化为8421BCD码，以提供数字显示电路所需要的编码输入。
2.2 锁存器
当只要有一个且为任意一个选手抢答输入信号产生时，锁存器电路被触发，在输出端产生相应的开关电平信息，同时为避免之后的抢答开关按钮也按下产生错乱，最先产生的输出电平变化又反馈回来将锁存器器锁定住，并保持输出的电平信息。
2.3 译码器
译码器的作用是将编码器输出的8421BCD码转化为数码管需要的逻辑状态。
2.4号码和时间显示器
数码显示管有发光的共阴二极管（LED）数码管，喇叭为高电平触发。
2.5分频器
通过脉冲来进行计时，用来抢答倒计时。
2.6报警器
当有选手抢答成功时或倒计时到十秒后，喇叭鸣响。
三总体电路RTL视图：

3,1各种模块的VHDL文本输入语言
1编码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bm IS
PORT(a,b,c,d,:IN STD_LOGIC;
RST1 :IN STD_LOGIC;
M: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END bm;
ARCHITECTURE one OF bm IS
SIGNAL M1: STD_LOGIC_VECTOR(1 TO 8);
BEGIN
M1<= a&b&c&d;
PROCESS(M1,RST1)
BEGIN
IF RST1='0' THEN
M<="0000";
ELSE
CASE M1 IS
WHEN "01111111" =>M<="0001";
WHEN "10111111" =>M<="0010";
WHEN "11011111" =>M<="0011";
WHEN "11101111" =>M<="0100";
WHEN OTHERS =>M<="0000";
END CASE;
END IF;
END PROCESS;
END one;
2.锁存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sc IS
PORT(S:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
RST2,EN2:IN STD_LOGIC;
C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END sc;
ARCHITECTURE TWO OF sc IS
BEGIN
PROCESS(S,EN2,RST2)
BEGIN
IF RST2='0' THEN
C<="0000";
ELSE IF EN2='1' THEN
C<=S;
END IF;
END IF;
END PROCESS;
END TWO;
3.译码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ym IS
PORT(Y:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED1:OUT STD_LOGIC_VECTOR(7 DOWNTO 1));
END ym ;
ARCHITECTURE THREE OF ym IS
BEGIN
PROCESS(Y)
BEGIN
CASE Y IS
WHEN "0001"=>LED1<="0000110";
WHEN "0010"=>LED1<="1011011";
WHEN "0011"=>LED1<="1001111";
WHEN "0100"=>LED1<="1100110";
WHEN OTHERS=>LED1<="0111111";
END CASE;
END PROCESS;
END THREE;
4.报警器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bj IS
PORT(BC,BS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LA:OUT STD_LOGIC);
END bj ;
ARCHITECTURE FOUR OF bj IS
BEGIN
PROCESS(BC,BS)
BEGIN
IF (((BC(0)OR BC(1) OR BC(2) OR BC(3))='1') OR BS="0000") THEN
LA<='1';
ELSE
LA<='0';
END IF;
END PROCESS;
END FOUR;
5.分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp IS
PORT(CLK1,RST3:IN STD_LOGIC;
S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END fp;
ARCHITECTURE FIVE OF fp IS
BEGIN
PROCESS(CLK1,RST3)
VARIABLE S1: STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE cnt:INTEGER RANGE 0 TO 29999999;
BEGIN
IF RST3='0' THEN S1:="1111";
ELSE IF (CLK1'EVENT AND CLK1='1') THEN
IF cnt<29999999 THEN
S1:=S1-1;
END IF;
END IF;
END IF;
S<=S1;
END PROCESS;
END FIVE;
6.显示器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xs IS
PORT(X:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED2:OUT STD_LOGIC_VECTOR(7 DOWNTO 1));
END xs;
ARCHITECTURE SIX OF xs IS
BEGIN
PROCESS(X)
BEGIN
CASE X IS
WHEN "0001"=>LED2<="0000110";
WHEN "0010"=>LED2<="1011011";
WHEN "0011"=>LED2<="1001111";
WHEN "0100"=>LED2<="1100110";
WHEN "0101"=>LED2<="1101101";
WHEN "0110"=>LED2<="1111101";
WHEN "0111"=>LED2<="0000111";
WHEN "1000"=>LED2<="1111111";
WHEN "1001"=>LED2<="1101111";
WHEN OTHERS=>LED2<="0111111";
END CASE;
END PROCESS;
END SIX;
7.顶层文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY qdq IS
PORT(Q1,Q2,Q3,Q4:IN STD_LOGIC;
RST,CLK: IN STD_LOGIC;
LED1,LED2:OUT STD_LOGIC_VECTOR(7 DOWNTO 1);
LA:OUT STD_LOGIC);
END qdq;
ARCHITECTURE SEVEN OF qdq IS
COMPONENT bm
PORT(a,c,c,d:IN STD_LOGIC;
RST1:IN STD_LOGIC;
M:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT sc
PORT(S:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
RST2,EN2:IN STD_LOGIC;
C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END COMPONENT;
COMPONENT ym
PORT(Y:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED1:OUT STD_LOGIC_VECTOR(7 DOWNTO 1));
END COMPONENT;
COMPONENT bj
PORT(BC,BS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LA:OUT STD_LOGIC);
END COMPONENT;
COMPONENT fp
PORT(CLK1,RST3:IN STD_LOGIC;
S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT xs
PORT(X:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED2:OUT STD_LOGIC_VECTOR(7 DOWNTO 1));
END COMPONENT;
SIGNAL A, C: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL B: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL D:STD_LOGIC;
SIGNAL E:STD_LOGIC;
SIGNAL F:STD_LOGIC;
BEGIN
D<=NOT(B(0) OR B(1) OR B(2) OR B(3));
E<=C(0) OR C(1) OR C(2) OR C(3);
F<=D AND E;
U1: bm PORT MAP(Q1,Q2,Q3,Q4,RST,A);
U2:sc PORT MAP(A,RST,F,B);
U3:ym PORT MAP(B,LED1);
U4:bj PORT MAP(B,C,LA);
U5:fp PORT MAP(CLK,RST,D, C);
U6:xs PORT MAP(C,LED2);
END SEVEN;