html编写抢答器,用veriloghdl编写四路抢答器.pptx

用veriloghdl编写四路抢答器

四路抢答器设计;抢答器为四路，20秒倒计时，抢到后显示锁定，计时停止，若提前抢答会在另外数码管显示抢答号码。在BASYS 2 开发板上可以实现;module qiang_da_qi(a_to_g,A_TO_D,clk,qiang_da,button,xuan );output wire [6:0]a_to_g;output wire [3:0]A_TO_D;input wire clk;//50MHz时钟wire [3:0]qian;wire [3:0]bai;wire [2:0]shi;wire [2:0]ge;wire cp;//1s时钟input wire [3:0]qiang_da;input button;wire suo_1;wire [2:0]bian_ma_cun;wire fankui;output wire xuan;shumaguan shumaguan0(a_to_g,A_TO_D,clk,qian,bai,shi,ge);cp_1s cp_1s0(clk,cp);xuan_shou xuan_shou0(qiang_da,button,suo_1,bian_ma_cun,fankui);wei_xuan wei_xuan0(bian_ma_cun,xuan,shi,ge);fuwei_kongzhi fuwei_kongzhi0(button,xuan);jishu_kongzhi jishu_kongzhi0(bai,qian,cp,suo_1,xuan,fankui);endmodule;module shumaguan(a_to_g,A_TO_D,clk,qian,bai,shi,ge);//数码管驱动output reg [6:0]a_to_g;output reg [3:0]A_TO_D;input wire clk;input wire [3:0]qian;input wire [3:0]bai;input wire [2:0]shi;input wire [2:0]ge;reg [3:0]duan;reg [1:0]wei;reg a;reg [16:0]q;always@(posedge clk)beginif(q==49999)beginq<=0;a<=~a;endelseq<=q+1;end;always@(*)//7位段译码case(duan)0:a_to_g=7'b0000001;1:a_to_g=7'b1001111;2:a_to_g=7'b0010010;3:a_to_g=7'b0000110;4:a_to_g=7'b1001100;5:a_to_g=7'b0100100;6:a_to_g=7'b0100000;7:a_to_g=7'b0001111;8:a_to_g=7'b0000000;9:a_to_g=7'b0000100;default:a_to_g=7'b0000001;endcase;always@(*)//4位位选译码case(wei)3:beginA_TO_D=4'b1110;duan=qian;end2:beginA_TO_D=4'b1101;duan=bai;end1:beginA_TO_D=4'b1011;duan=shi;end0:beginA_TO_D=4'b0111;duan=ge;enddefault:A_TO_D=4'b1110;endcasealways@(posedge a)//四个状态循环if(wei==3)wei<=0;elsewei<=wei+1;

endmodule;module cp_1s(clk,a); //提供1秒脉冲input wire clk;output reg a;reg [25:0]q;always@(posedge clk) beginif(q=beginq<=0;a<=~a;end elseq<=q+1;endendmodule;module xuan_shou(qiang_da,qing_ling,suo_1,bian_ma_cun,fankui);//选手抢答模块，某选手抢答后结果锁存input wire [3:0]qiang_da;reg [2:0]bian_ma;wire suo;input wire qing_ling;input wire fankui;outp