杭电数字电路课程设计-实验十四-基本寄存器设计实验

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module jicunqi(OE,CLR,CLK,Q,D);
input[3:0] D;
input OE,CLR,CLK;
output reg[3:0] Q;
always@(OE or CLR or CLK)
if(OE)
begin
Q[3]=0;Q[2]=0;Q[1]=0;Q[0]=0;
end
else if(CLR==1)
begin
Q[3]=0;Q[2]=0;Q[1]=0;Q[0]=0;
end
else if(CLR==0&&CLK==1)
begin
Q[3]=D[3];
Q[2]=D[2];
Q[1]=D[1];
Q[0]=D[0];
end
endmodule

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	initial begin
OE = 1;
CLR = 0;
CLK = 0;
D=4'b1100;
#100;
OE = 0;
CLR = 0;
CLK = 1;
D=4'b1100;
#100;
OE = 0;
CLR = 0;
CLK = 0;
D=4'b1100;
#100;
OE = 0;
CLR = 1;
CLK = 0;
D=4'b1100;
#100;
OE = 0;
CLR = 0;
CLK = 1;
D=4'b1100;
#100;
OE = 0;
CLR = 1;
CLK = 1;
D=4'b1100;
#100;
OE = 0;
CLR = 0;
CLK = 1;
D=4'b0011;
#100;
end
endmodule

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NET "D[3]" IOSTANDARD = LVCMOS18;
NET "D[2]" IOSTANDARD = LVCMOS18;
NET "D[1]" IOSTANDARD = LVCMOS18;
NET "D[0]" IOSTANDARD = LVCMOS18;
NET "Q[3]" IOSTANDARD = LVCMOS18;
NET "Q[2]" IOSTANDARD = LVCMOS18;
NET "Q[1]" IOSTANDARD = LVCMOS18;
NET "Q[0]" IOSTANDARD = LVCMOS18;
NET "CLK" IOSTANDARD = LVCMOS18;
NET "CLR" IOSTANDARD = LVCMOS18;
NET "OE" IOSTANDARD = LVCMOS18;
NET "D[3]" PULLDOWN;
NET "D[2]" PULLDOWN;
NET "D[1]" PULLDOWN;
NET "D[0]" PULLDOWN;
NET "CLR" PULLDOWN;
NET "CLK" PULLDOWN;
NET "OE" PULLDOWN;
NET "D[3]" LOC = T3;
NET "D[2]" LOC = U3;
NET "D[1]" LOC = T4;
NET "D[0]" LOC = V3;
NET "Q[3]" LOC = R1;
NET "Q[2]" LOC = P2;
NET "Q[1]" LOC = P1;
NET "Q[0]" LOC = N2;
NET "CLK" LOC = W4;
NET "CLR" LOC = v4;
NET "OE" LOC = Y6;
NET "CLR" LOC = V4;