一个简单的五进制加法计数器

1.1 verilog代码

module counter_fsm(clk,rst_n,Z);
input clk,rst_n;
output reg Z;
reg [2:0] pre_state,next_state;
parameter s0=3’b000,s1=3’b001,s2=3’b010,s3=3’b011,s4=3’b100;
always@(posedge clk or negedge rst_n)
if(!rst_n) pre_state<=s0;
else pre_state<=next_state;
always@(pre_state) begin
next_state=3’bxxx;
Z=1’b0;
case(pre_state)
s0:begin next_state=s1;Z=1’b0;end
s1:begin next_state=s2;Z=1’b0;end
s2:begin next_state=s3;Z=1’b0;end
s3:begin next_state=s4;Z=1’b0;end
s4:begin next_state=s0;Z=1’b1;end
default:begin next_state=s0; end
endcase
end
endmodule

1.2 testbench

`timescale 1ns/1ns
module counter_fsm_tb;
reg clk,rst_n;
wire Z;
counter_fsm U1(.clk(clk),.rst_n(rst_n),.Z(Z));
always #10 clk=~clk;
initial begin
clk=1’b0;
rst_n=1’b1;
#10 rst_n=1’b0;
#10 rst_n=1’b1;
end
endmodule

1.3 wave

最后

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