verilog 通过function 递归, 数据拓展

module test();

  parameter NBYTES      = 4   ;

  reg [511:0] tb_stream       ;

  reg [511 : 0] realstream    ;

  reg [31  : 0]        packet ;

  initial begin

      // packet = $random;

      packet = 'ha5;

      tb_stream = {NBYTES{packet[7:0]}};

      $display($realtime,,"packet = %h, realstream = %0h [start]",packet,tb_stream);

      realstream = getrealstream(tb_stream,NBYTES);

      $display($realtime,,"packet = %h, realstream = %0h [done]",packet,tb_stream);

  end

  function [511:0] getrealstream; // defualt is wire

    input [511:0] stream;

    input nbytes;

    integer nbytes;

    integer i;

    begin

            $display($realtime,,"stream = %0h ", stream);

        for(i= 0; i < 512; i = i+1)

        begin

            if(i < nbytes*8) getrealstream[i] = stream[i];

            else getrealstream[i] = 1'b0;

            $display($realtime,,"[i] = %3d , getrealstream[i] = %0h, getrealstream = %h",i,getrealstream[i],getrealstream);

        end

    end

  endfunction

endmodule

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