HDLBits Verilog编程题127 存水放水状态机

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HDLBits 存水放水状态机-Exams/ece241 2013 q4

状态转换图

原题链接：https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q4
说明：
水位在S1下(S1,S2,S3=0)：fr1,fr2,fr3,dfr=1;
水位在S2和S1之间(S1=1,S2,S3=0)：fr1, fr2=1;
水位在S3和S2之间(S1,S2=1,S3=0)：fr1=1;
水位超过S3(S1,S2,S3=1)：fr1,fr2,fr3,dfr=0。
并要求前一时刻的水位高于当前时刻水位时（即放水过程）dfr=1。
本思路中使用了6个状态位，为直观方便将转换条件单独提出。

复制代码

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    
    parameter S0 = 4'd0;
    parameter S1 = 4'd1;
    parameter S2 = 4'd2;
    parameter S3 = 4'd3;
    parameter S4 = 4'd4;
    parameter S5 = 4'd5;

reg [2:0] state_c, state_n;
    wire S02S1, S12S0, S12S2, S22S3, S22S5, S32S4, S42S5, S42S3, S52S0, S52S2;
    always@(posedge clk) begin
        if(reset)
            state_c<=S0;
        else
            state_c <= state_n;
    end
    
    assign S02S1 = s[3:1] == 3'b001 && state_c == S0;
    assign S12S0 = s[3:1] == 3'b000 && state_c == S1;
    assign S12S2 = s[3:1] == 3'b011 && state_c == S1;
    assign S22S3 = s[3:1] == 3'b111 && state_c == S2;
    assign S22S5 = s[3:1] == 3'b001 && state_c == S2;
    assign S32S4 = s[3:1] == 3'b011 && state_c == S3;
    assign S42S5 = s[3:1] == 3'b001 && state_c == S4;
    assign S42S3 = s[3:1] == 3'b111 && state_c == S4;
    assign S52S0 = s[3:1] == 3'b000 && state_c == S5;
    assign S52S2 = s[3:1] == 3'b011 && state_c == S5;
    always@(*) begin
        case(state_c)
            S0:begin
                if(S02S1)
                    state_n = S1;
                else
                    state_n = state_c;
            end
            S1:begin
                if(S12S2)
                    state_n = S2;
                else if(S12S0)
                    state_n = S0;
                else
                    state_n = state_c;
            end            
            S2:begin
                if(S22S3)
                    state_n = S3;
                else if(S22S5)
                    state_n = S5;
                else
                    state_n = state_c;
            end                    
            S3:begin
                if(S32S4)
                    state_n = S4;
                else
                    state_n = state_c;
            end
            S4:begin
                if(S42S5)
                    state_n = S5;
                else if(S42S3)
                    state_n = S3;
                else
                    state_n = state_c;
            end   
            S5:begin
                if(S52S0)
                    state_n = S0;
                else if(S52S2)
                    state_n = S2;
                else
                    state_n = state_c;
            end
        endcase
    end

assign fr3 = state_c == S0;
    assign fr2 = state_c == S0 || state_c == S1 || state_c == S5;
    assign fr1 = state_c == S0 || state_c == S1 || state_c == S2 || state_c==S4 || state_c==S5;
    assign dfr = state_c == S0 || state_c == S4 || state_c == S5;
    
endmodule

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module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    
    parameter S0 = 4'd0;
    parameter S1 = 4'd1;
    parameter S2 = 4'd2;
    parameter S3 = 4'd3;
    parameter S4 = 4'd4;
    parameter S5 = 4'd5;

    reg [2:0] state_c, state_n;
    wire S02S1, S12S0, S12S2, S22S3, S22S5, S32S4, S42S5, S42S3, S52S0, S52S2;
    always@(posedge clk) begin
        if(reset)
            state_c<=S0;
        else
            state_c <= state_n;
    end
    
    assign S02S1 = s[3:1] == 3'b001 && state_c == S0;
    assign S12S0 = s[3:1] == 3'b000 && state_c == S1;
    assign S12S2 = s[3:1] == 3'b011 && state_c == S1;
    assign S22S3 = s[3:1] == 3'b111 && state_c == S2;
    assign S22S5 = s[3:1] == 3'b001 && state_c == S2;
    assign S32S4 = s[3:1] == 3'b011 && state_c == S3;
    assign S42S5 = s[3:1] == 3'b001 && state_c == S4;
    assign S42S3 = s[3:1] == 3'b111 && state_c == S4;
    assign S52S0 = s[3:1] == 3'b000 && state_c == S5;
    assign S52S2 = s[3:1] == 3'b011 && state_c == S5;
    always@(*) begin
        case(state_c)
            S0:begin
                if(S02S1)
                    state_n = S1;
                else
                    state_n = state_c;
            end
            S1:begin
                if(S12S2)
                    state_n = S2;
                else if(S12S0)
                    state_n = S0;
                else
                    state_n = state_c;
            end            
            S2:begin
                if(S22S3)
                    state_n = S3;
                else if(S22S5)
                    state_n = S5;
                else
                    state_n = state_c;
            end                    
            S3:begin
                if(S32S4)
                    state_n = S4;
                else
                    state_n = state_c;
            end
            S4:begin
                if(S42S5)
                    state_n = S5;
                else if(S42S3)
                    state_n = S3;
                else
                    state_n = state_c;
            end   
            S5:begin
                if(S52S0)
                    state_n = S0;
                else if(S52S2)
                    state_n = S2;
                else
                    state_n = state_c;
            end
        endcase
    end

    assign fr3 = state_c == S0;
    assign fr2 = state_c == S0 || state_c == S1 || state_c == S5;
    assign fr1 = state_c == S0 || state_c == S1 || state_c == S2 || state_c==S4 || state_c==S5;
    assign dfr = state_c == S0 || state_c == S4 || state_c == S5;
    
endmodule