概述
12-hour clock countclock
Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).
reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.
The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
always @(posedge clk)
begin
if(reset)
pm<=0;
else if(hh==8'h11&&mm==8'h59&&ss==8'h59)
pm<=~pm;
else pm<=pm;
end
reg [1:0]cout;
reg [1:0]cout59;
s_one_bit_cont ss1(clk,reset,ena,ss,cout[0]);
m_one_bit_cont mm1(clk,reset,ena&&cout[0],mm,cout[1]);
h_two_bit_cont hh1(clk,reset,ena&&cout[0]&&cout[1],hh);
endmodule
module h_two_bit_cont(
input clk,reset,ena,
output reg [7:0] ss
);
always @(posedge clk)
begin
if(reset==1)
ss<=8'h12;
else if(ena)
begin
if(ss==8'h12)
ss<=8'h01;
else
begin
if(ss==8'h09)
ss<=8'h10;
else
ss<=ss+1;
end
end
end
endmodule
module s_one_bit_cont(
input clk,reset,ena,
output reg[7:0] ms,
output cout
);
always@(posedge clk)
begin
//cout<=0;
if(reset)
ms<=0;
else if(ena)
begin
if(ms==8'h59)
begin
ms<=0;
end
else if(ms[3:0]==4'h9)
begin
ms[3:0]<=0;
ms[7:4]<=ms[7:4]+1;
end
else
ms[7:0]<=ms[7:0]+1;
end
if (ms == 8'h58)
cout<=1;
else
cout<=0;
end
endmodule
module m_one_bit_cont(
input clk,reset,ena,
output reg[7:0] ms,
output cout
);
always@(posedge clk)
begin
if(reset)
ms<=0;
else if(ena)
begin
if(ms==8'h59)
begin
ms<=0;
end
else if(ms[3:0]==4'h9)
begin
ms[3:0]<=0;
ms[7:4]<=ms[7:4]+1;
end
else
ms[7:0]<=ms[7:0]+1;
end
if (ms == 8'h59)
cout<=1;
else cout<=0;
end
endmodule
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