FPGA应用实验设计（二）—异步清零4位二进制计数器一、实验目的二、实验内容三、实验设计及结果四、实验思考

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我是靠谱客的博主甜甜水池，这篇文章主要介绍FPGA应用实验设计（二）—异步清零4位二进制计数器一、实验目的二、实验内容三、实验设计及结果四、实验思考，现在分享给大家，希望可以做个参考。

一、实验目的

1、了解时序电路的 VHDL 语言设计方法。
2、掌握同步计数器的设计方法，设计任意进制的计数器。

二、实验内容

1、用VHDL设计一个上升沿触发、异步清零的4位二进制计数器。

三、实验设计及结果

1、实验设计

本实验设计一个上升沿触发、异步清零的4位二进制计数器，运用if语句达到预期目标。预设初始状态为A=”0000”,设计当复位为有效电平时计数器清零，当时钟信号发生，并处于上升沿时，计数器开始工作。
当复位键为有效电平，即RESET=’0’时，输出Y=”0000”,此时达到异步清零的目标；当时钟信号发生，且在其上升沿，及CLK=’1’时，A+“0001”，进而输出Y达到在上升沿进行计数的目标。

2、实验代码

复制代码

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity yibu is
port(
		A:in std_logic_vector(3 downto 0);
		CLK: in std_logic;
		RESET: in std_logic;
		Y: out std_logic_vector(3 downto 0)
		);
end yibu;
architecture Q of yibu is
begin
		process(A,CLK,RESET)
		begin
			if RESET ='0' then
				Y<= "0000";
			elsif CLK'event and CLK='1' then
				Y <= A +"0001";
			end if;
		end process;
end Q;

仿真代码（init及always进程）

复制代码

init : PROCESS                                      
BEGIN  
		RESET <='0';
		wait for 200 ns;
		A <= "0000";
		RESET <='1';	
		wait for 200 ns;	
		A <= "0001";
		RESET <='1';	
		wait for 200 ns;
		A <= "0010";
		RESET <='1';
		wait for 200 ns;
		A <= "0011";
		RESET <='1';	
		wait for 200 ns;
		A <= "0100";
		RESET <='1';	
		wait for 200 ns;
		A <= "0101";
		RESET <='1';	
		wait for 200 ns;
		A <= "0110";
		RESET <='1';	
		wait for 200 ns;
		A <= "0111"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1000"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1001";
		RESET <='1';	
		wait for 200 ns;
		A <= "1010"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1011"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1100"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1101"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1110"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1111"; 
		RESET <='1';
		WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                                                                 
BEGIN                                                         
		CLK <= '0';
		wait for 100 ns;
		CLK <= '1';
		wait for 100 ns;   
END PROCESS always;                                          
END yibu_arch;

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init : PROCESS                                      
BEGIN  
		RESET <='0';
		wait for 200 ns;
		A <= "0000";
		RESET <='1';	
		wait for 200 ns;	
		A <= "0001";
		RESET <='1';	
		wait for 200 ns;
		A <= "0010";
		RESET <='1';
		wait for 200 ns;
		A <= "0011";
		RESET <='1';	
		wait for 200 ns;
		A <= "0100";
		RESET <='1';	
		wait for 200 ns;
		A <= "0101";
		RESET <='1';	
		wait for 200 ns;
		A <= "0110";
		RESET <='1';	
		wait for 200 ns;
		A <= "0111"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1000"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1001";
		RESET <='1';	
		wait for 200 ns;
		A <= "1010"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1011"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1100"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1101"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1110"; 
		RESET <='1';
		wait for 200 ns;
		A <= "1111"; 
		RESET <='1';
		WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                                                                 
BEGIN                                                         
		CLK <= '0';
		wait for 100 ns;
		CLK <= '1';
		wait for 100 ns;   
END PROCESS always;                                          
END yibu_arch;

3、实验结果

在这里插入图片描述
注：仿真结果图中输入A存在红色线状态：在代码中开始未设置A的初始数值，而当RESET为有效电平时，此时A置零，则开始有确切数值。

四、实验思考

仿真时如何改变时钟频率？如果改变时钟频率，计数器实验的结果有何变化？
仿真时在vht文件中always进程中，通过时钟信号CLK处于不同状态是的时延改变时钟频率；若时钟频率过高，则对于A的状态读取不完全，使得输出出现错误；若时钟频率过低，则存在时钟信号出发而计数器未及响应，则响应时刻出现输出结果未改变的状况，使得计数器存在误差。