VHDL：时序逻辑电路实验-两位16进制加减可逆计数器

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概述

工程包下载：【时序逻辑电路实验：手动设置8位检测码的序列检测器】

分析：

1、两位16进制数可通过2个七段数码管显示；

2、通过定义sw作为加减的开关，控制加减操作。

VHDL代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncommemt the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;


entity counter6 is
port(clk1,clk2,din,en,rst: in std_logic;
     dout: out std_logic_vector(7 downto 0);
     scan: out std_logic_vector(5 downto 0));
end counter6;

architecture Behavioral of counter6 is
signal c,f1,f2,fclk,fd,f: std_logic:='0';
signal data1,data2,dataout,fclk1:std_logic_vector(3 downto 0);
signal temp:std_logic_vector(2 downto 0);
begin
    process(clk1)
    begin
        if clk1'event and clk1='1' then
            fclk1<=fclk1+1;
    end if;
    end process;

fd<=fclk1(3);

    process(fd)
    begin
        if fd'event and fd='1' then
             if din='0' then c<='1';
             else c<='0';
             end if;
        end if;
    end process;

    f1<=(c and en) or (not en);


    process(f1)
    begin
        if rst='1' then data1<="0000";
        elsif f1'event and f1='1' then
          if en='1' then
             if data1="1111" then
                  f2<='1';   data1<="0000";
             else     data1<=data1+1;   f2<='0';
             end if;
          else  
             if data1="0000" then
                  f2<='1';  data1<="1111";   data2<=data2-1;
             else     data1<=data1-1;  f2<='0';
             end if;
          end if;
        end if;
    end process;


    process(f2)
    begin
        if rst='1' then data2<="0000";
        elsif f2'event and f2='1' then
           if en='1' then
             if data2="1111" then
                 data2<="0000";
             else     data2<=data2+1;
             end if;
           else  
             if data2="0000" then
                  data2<="1111";
             else  data2<=data2-1;
             end if;
           end if;
        end if;
    end process;


   process(clk2)
    begin
 if clk2'event and clk2='1' then
   if temp="101" then temp<="000";
   else temp<=temp+1;
   end if;
   end if;
  end process;

process(temp)
  begin
   case temp is
   when "000"=> dataout<=data1;scan<="000001";
   when "001"=> dataout<=data2;scan<="000010";
   when others=>null;
   end case;
case dataout is
   when "0000"=>dout<="00111111";
   when "0001"=>dout<="00000110";
   when "0010"=>dout<="01011011";
   when "0011"=>dout<="01001111";
   when "0100"=>dout<="01100110";
   when "0101"=>dout<="01101101";
   when "0110"=>dout<="01111101";
   when "0111"=>dout<="00000111";
   when "1000"=>dout<="01111111";
   when "1001"=>dout<="01101111";
   when "1010"=>dout<="01110111";
   when "1011"=>dout<="01111100";
   when "1100"=>dout<="00111001";
   when "1101"=>dout<="01011110";
   when "1110"=>dout<="01111001";
   when "1111"=>dout<="01110001";
   when others=>dout<="00000000";
end case;
end process;
end Behavioral;