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module top_module (
	input a,
	input b,
	input c,
	input d,
	output out,
	output out_n );
	wire w1, w2;		// Declare two wires (named w1 and w2)
	assign w1 = a&b;	// First AND gate
	assign w2 = c&d;	// Second AND gate
	assign out = w1|w2;	// OR gate: Feeds both 'out' and the NOT gate
	assign out_n = ~out;	// NOT gate
endmodule

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wire [7:0] w;         // 8-bit wire
reg  [4:1] x;         // 4-bit reg
output reg [0:0] y;   // 1-bit reg that is also an output port (this is still a vector)
input wire [3:-2] z;  // 6-bit wire input (negative ranges are allowed)
output [3:0] a;       // 4-bit output wire. Type is 'wire' unless specified otherwise.
wire [0:7] b;         // 8-bit wire where b[0] is the most-significant bit.

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//同步复位
always @(posedge clk) begin
    if(reset == 1) begin
        //reset
    end
end
//异步复位
always @(posedge clk,posedge areset) begin
    if(areset == 1) begin
        //reset
    end
end

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always @(*) begin     //这是一个组合逻辑
    case (in)
      1'b1: begin 
               out = 1'b1;  
            end
      1'b0: out = 1'b0;
      default: out = 1'bx;
    endcase //一定记得写endcase
end

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module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
    always @(*) begin
        casez (in)
            8'bzzzzzzz1 : pos = 0;
            8'bzzzzzz1z : pos = 1;
            8'bzzzzz1zz : pos = 2;
            8'bzzzz1zzz : pos = 3;
            8'bzzz1zzzz : pos = 4;
            8'bzz1zzzzz : pos = 5;
            8'bz1zzzzzz : pos = 6;
            8'b1zzzzzzz : pos = 7;
            default: pos =0;
        endcase
    end   
endmodule

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module top_module (
	input [254:0] in,
	output reg [7:0] out
);
    always @(*) begin	//组合逻辑always块
		out = 0;        //一定要初始化为0
		for (int i=0;i<255;i++)
			out = out + in[i];
	end
endmodule

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	genvar i;//只能用genvar作为循环变量
    generate
        for (i=1;i<99;i=i+1) begin: add_loop//这个名字是必须的
            mod_name instance_name(......);//括号里写由i推出的信号
       	end
    endgenerate

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module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    genvar i;
    wire [99:0]cout1;
    bcd_fadd mod1(a[3:0],b[3:0],cin,cout1[0],sum[3:0]);
    generate
        for (i=1;i<99;i=i+1) begin: addloop
            bcd_fadd mod2(a[(4*i+3):(4*i)],b[(4*i+3):(4*i)],cout1[i-1],cout1[i],sum[(4*i+3):(4*i)]);
        end
    endgenerate
    bcd_fadd mod3(a[399:396],b[399:396],cout1[98],cout,sum[399:396]);
endmodule

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    reg state, next_state;

	//第一段：
	always @(*) begin    //一个组合逻辑always块，用于写状态转换逻辑，当in改变时，next_state将立即改变。
        case(state)
            A: next_state = f(in)//关于in的函数
            B: next_state = f(in)
            ...    
        endcase
    end
                
	//第二段（异步）：
    always @(posedge clk, posedge areset) begin    
        if(areset == 1) begin
            state <= 0;//reset
        end
        else state <= next_state;
    end
	//第二段（同步）：
    always @(posedge clk) begin   
        if(reset == 1) begin
            state <= 0;//reset
        end
        else state <= next_state;
    end
            
    //第三段（assign法）
            assign out = (state == ...);//判断state
	//第三段（组合逻辑always块法）
    always@(*) begin
        case (state)
            A: {out3,out2,out1} = 3'b111;
            B: {out3,out2,out1} = 3'b110;//对每一种状态输出
            ...
        endcase
    end

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    //第三段（assign法）
    assign out = f(state,in);//关于state和in的函数
    //第三段（组合逻辑always块法）
    always@(*) begin
        case ({state,in})
            4'b0000: {out3,out2,out1} = 3'b111;
            4'b0001: {out3,out2,out1} = 3'b110;//对每一种state与in做输出
            ...
    end