一、Mux256to1

        Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

1、通过底层模块四选一搭建16选1选择器，同理搭建256选1选择器。

module c256to1(
input [255:0] in,
input [7:0] sel,
output out );
genvar i;
wire [15:0] tmp1;
generate
for(i=0;i<=16;i=i+1'b1)begin:s1
if(i==16)begin
c16_1_module u16(
.in(tmp1[15:0]),
.sel(sel[7:4]),
.out(out));
end
else begin
c16_1_module u_16to1_module(
.in(in[16*i+15:16*i]),
.sel(sel[3:0]),
.out(tmp1[i]));
end
end
endgenerate
endmodule
module c4_1_module(
input [3:0] in,
input [1:0] sel,
output reg out);
always@(*)begin
case(sel)
2'b00:out=in[0];
2'b01:out=in[1];
2'b10:out=in[2];
2'b11:out=in[3];
default:out=4'h0;
endcase
end
endmodule
module c16_1_module(
input [15:0] in,
input [3:0] sel,
output out);
wire
[3:0] tmp ;
c4_1_module u0(
.in(in[3:0]),
.sel(sel[1:0]),
.out(tmp[0])
);
c4_1_module u1(
.in(in[7:4]),
.sel(sel[1:0]),
.out(tmp[1])
);
c4_1_module u2(
.in(in[11:8]),
.sel(sel[1:0]),
.out(tmp[2])
);
c4_1_module u3(
.in(in[15:12]),
.sel(sel[1:0]),
.out(tmp[3])
);
c4_1_module u4(
.in(tmp[3:0]),
.sel(sel[3:2]),
.out(out)
);
endmodule

2、答案解析

• With this many options, a case statement isn't so useful.
• Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. In particular, selecting one bit out of a vector using a variable index will work.module top_module( input [255:0] in, input [7:0] sel, output out ); assign out = in[sel]; endmodule

module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel]; //惊到了，还可以这么使用。
endmodule

一条assign语句解决。

二、Mux256to1 4-bit v

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

1、答案解析

• With this many options, a case statement isn't so useful.
• Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. It's not always good at this. An error saying "... is not a constant" means it couldn't prove that the select width is constant. In particular, in[ sel*4+3 : sel*4 ] does not work.
• Bit slicing ("Indexed vector part select", since Verilog-2001) has an even more compact syntax.

module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
// We can't part-select multiple bits without an error, but we can select one bit at a time,
// four times, then concatenate them together.
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
// Alternatively, "indexed vector part select" works better, but has an unfamiliar syntax:
// assign out = in[sel*4 +: 4];
// Select starting at index "sel*4", then select a total width of 4 bits with increasing (+:) index number.
// assign out = in[sel*4+3 -: 4];	// Select starting at index "sel*4+3", then select a total width of 4 bits with decreasing (-:) index number.
// Note: The width (4 in this case) must be constant.
endmodule

2、代码简单，实现功能一样，但资源利用率不相同。（晚上用Vivado试一试）

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