Simulink HDL Coder FPGA初级开发实践（二） LED流水灯

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
// -------------------------------------------------------------
// 
// File Name: hdlsrcled_mbdLED_HDL.v
// Created: 2022-03-09 17:06:11
// 
// Generated by MATLAB 9.10 and HDL Coder 3.18
// 
// 
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: 0.2
// Target subsystem base rate: 0.2
// 
// 
// Clock Enable  Sample Time
// -- -------------------------------------------------------------
// ce_out        0.2
// -- -------------------------------------------------------------
// 
// 
// Output Signal                 Clock Enable  Sample Time
// -- -------------------------------------------------------------
// out                           ce_out        0.2
// out1                          ce_out        0.2
// out2                          ce_out        0.2
// out3                          ce_out        0.2
// -- -------------------------------------------------------------
// 
// -------------------------------------------------------------


// -------------------------------------------------------------
// 
// Module: LED_HDL
// Source Path: led_mbd/LED_HDL
// Hierarchy Level: 0
// 
// -------------------------------------------------------------

`timescale 1 ns / 1 ns

module LED_HDL  // 由于使用的开发板是双端时钟，这里需要将默认生成的时钟稍微修改一下
          (clk_p,
          clk_n,
           reset,

           out,
           out1,
           out2,
           out3);


  input   clk_n;
  input  clk_p; 
  input   reset;

  output  out;
  output  out1;
  output  out2;
  output  out3;


  wire enb;
  wire [31:0] PlusOne_out1;  // uint32
  wire [31:0] threshold_out1;  // uint32
  wire [31:0] Constant5_out1;  // uint32
  wire [31:0] Return_0_out1;  // uint32
  reg [31:0] Delay_out1;  // uint32
  wire [31:0] Add_out1;  // uint32
  wire GreaterThan_Threshold_relop1;
  wire switch_compare_1;
  reg [31:0] Delay1_out1;  // uint32
  wire [31:0] Light_on_out1;  // uint32
  wire GreaterThan2_relop1;


IBUFDS sys_clk_ibufgds  // 这部分需要自行添加，用于生成单端时钟
       (
         .O              (clk                  ),
         .I              (clk_p                ),
         .IB             (clk_n                )
       );

  assign enb = 1;

  assign PlusOne_out1 = 32'b00000000000000000000000000000001;  // 加1


  assign threshold_out1 = 32'd200_000_000;  // 计数到1s


  assign Constant5_out1 = 32'b00000000000000000000000000000000;  //归零


  always @(posedge clk or posedge reset)
    begin : Delay_process
      if (reset == 1'b0) begin
        Delay_out1 <= 32'b00000000000000000000000000000000;
      end
      else begin
        if (enb) begin
          Delay_out1 <= Return_0_out1;
        end
      end
    end


  assign Add_out1 = Delay_out1 + PlusOne_out1;


  assign GreaterThan_Threshold_relop1 = Add_out1 > threshold_out1;


  assign switch_compare_1 = GreaterThan_Threshold_relop1 > 1'b0;



  assign Return_0_out1 = (switch_compare_1 == 1'b0 ? Add_out1 :
              Constant5_out1);


  always @(posedge clk or posedge reset)
    begin : Delay1_process
      if (reset == 1'b0) begin
        Delay1_out1 <= 32'b00000000000000000000000000000000;
      end
      else begin
        if (enb) begin
          Delay1_out1 <= Return_0_out1;
        end
      end
    end


  assign Light_on_out1 = 32'd100_000_000;


  assign GreaterThan2_relop1 = Delay1_out1 > Light_on_out1;


  assign out = GreaterThan2_relop1;

  assign out1 = GreaterThan2_relop1;

  assign out2 = GreaterThan2_relop1;

  assign out3 = GreaterThan2_relop1;



endmodule  // LED_HDL