hdlbits:Count clock-12_hour clock 答案参考

 思路:是从秒的后四位开始推,知道时针的十位

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    reg pm_temp;
    wire mmm;
   
    always@(posedge clk)
        if(reset)begin
            ss[3:0]<=0;
    		
            //pm<=0;
        end
    else if(ena==0)
        ss[3:0]<=ss[3:0];
    else if(ss[3:0]==4'd9)
        ss[3:0]<=0;
    else
        ss[3:0]<=ss[3:0]+1'd1;
    
    always@(posedge clk)
        if(reset)
            ss[7:4]<=0;
    		
    else if(ss[3:0]==4'd9&&ss[7:4]<4'd5&&ena==1'd1)
        ss[7:4]<=ss[7:4]+1'd1;
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5)
        ss[7:4]<=0;
    /*else if(ena==0)
        ss[7:4]<=ss[7:4];*/
    else
        ss[7:4]<=ss[7:4];
    always@(posedge clk)
        if(reset)
            
            mm[3:0]<=0;
            
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]<4'd9)
        mm[3:0]<=mm[3:0]+1'd1;
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9)
        mm[3:0]<=0;
    else
        mm[3:0]<=mm[3:0];
                    
    always@(posedge clk)
        if(reset)
            mm[7:4]<=0;    
  else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]<4'd5)
      mm[7:4]<=mm[7:4]+1'd1;
 else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5)
       mm[7:4]<=0;
    else
          mm[7:4]<=mm[7:4];
                    
                    
           always@(posedge clk)
        if(reset)
           
            hh[3:0]<=2;
                    
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5&&hh[7:4]==4'd0&&hh[3:0]<4'd9)
       hh[3:0]<=hh[3:0]+1'b1;
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5&&hh[7:4]==1'd1&&hh[3:0]<4'd2)
        hh[3:0]<=hh[3:0]+1'b1;
                    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5&&hh[3:0]==4'd2&&hh[7:4]==4'd1)
                        hh[3:0]<=1'd1;
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5&&hh[3:0]==4'd9)
        hh[3:0]<=0;
                    else
                        hh[3:0]<=hh[3:0];
                    
		always@(posedge clk)
        if(reset)
           
            hh[7:4]<=1;
            
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5&&hh[3:0]==4'd9&& hh[7:4]==4'd0)
                        hh[7:4]<=hh[7:4]+1'd1;
       						 
    else if(ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5&&hh[3:0]==4'd2&&hh[7:4]==4'd1)
        hh[7:4]<=1'd0;
                    else
                        hh[7:4]<=hh[7:4];
    always@(posedge clk)
        if(reset)
            pm_temp<=0;
    else if(mmm)
        pm_temp<=~pm_temp;
    assign mmm = ss[3:0]==4'd9&&ss[7:4]==4'd5&&mm[3:0]==4'd9&&mm[7:4]==4'd5&&hh[3:0]==4'd1&&hh[7:4]==4'd1;
    assign pm=pm_temp;
endmodule

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