HDLBits-Counter 1000

题目：

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

module bcdcount (
input clk,
input reset,
input enable,
output reg [3:0] Q
);

题目理解：

将1kHz时钟分频成1Hz，计数器应从0到999计数循环，每计数到999，出来一个高脉冲，于是实现了1Hz的时钟输出。从0到999计数，由于是模10计数器，所以一共需要3个计数器，分别代表个、十、百位。

正确代码：

注解：

counter0，即代表个位的计数器，正常状态下应该一直计数，所以c_enable[0] = ~reset；counter1，即代表十位的计数器，只有个位为9时才会计数一次，所以c_enable[1] = (~reset) && (Q0 == 4'd9)；counter2，即代表百位的计数器，只有当个位和十位都为9时才会计数一次，所以c_enable[2] = (~reset) && (Q0 == 4'd9) && (Q1 == 4'd9)。

所犯错误：

认为当十位为9时，counter2就会计数一次，所以写成了c_enable[2] = (~reset) && (Q1 == 4'd9)。

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