左移寄存器vhdl_vhdl - VHDL中移位寄存器的结构设计 - 堆栈内存溢出

您的负载(WriteShift ='1'和en ='1')也不起作用。

有一个设计缺陷，您使用4个输入与非门，您需要一个2：1多路复用器来为移位寄存器中的四个LSB在Din和q位之间进行选择。

通过使用三个2个输入NOR门创建2：1多路复用器，可以解决此问题：

architecture behavioral of shiftregis is

component notgate

port (

in0: in std_logic;

out0: out std_logic

);

end component;

-- component nand4gate

-- port (

-- i0: in std_logic;

-- i1: in std_logic;

-- i2: in std_logic;

-- i3: in std_logic;

-- bitout: out std_logic

-- );

-- end component;

component nor2gate

port (

i0: in std_logic;

i1: in std_logic;

bitout: out std_logic

);

end component;

component d_flipflop

port (

din: in std_logic;

en: in std_logic;

q: out std_logic;

reset: in std_logic;

clk: in std_logic

);

end component;

signal q4, q3, q2, q1, in3, in2, in1, in0, notws: std_logic;

signal nor2g0a, nor2g0b: std_logic; -- ADDED

signal nor2g1a, nor2g1b: std_logic; -- ADDED

signal nor2g2a, nor2g2b: std_logic; -- ADDED

signal nor2g3a, nor2g3b: std_logic; -- ADDED

begin

ff4:

d_flipflop

port map (

din => din(4),

en => en,

q => q4,

reset => reset,

clk => clock

);

ff3:

d_flipflop

port map (

din => in3,

en => en,

q => q3,

reset => reset,

clk => clock

);

ff2:

d_flipflop

port map (

din => in2,

en => en,

q => q2,

reset => reset,

clk => clock

);

ff1:

d_flipflop

port map (

din => in1,

en => en,

q => q1,

reset => reset,

clk => clock

);

ff0:

d_flipflop

port map (

din => in0,

en => en,

q => q(0),

reset => reset,

clk => clock

);

notg4:

notgate

port map (

in0 => writeshift,

out0 => notws

);

-- norg3:

-- nand4gate

-- port map (

-- i0 => din(3),

-- i1 => notws,

-- i2 => writeshift,

-- i3 => q4,

-- bitout => in3

-- );

norg3a:

nor2gate

port map (

i0 => din(3),

i1 => writeshift,

bitout => nor2g3a

);

norg3b:

nor2gate

port map (

i0 => notws,

i1 => q4,

bitout => nor2g3b

);

nor3gc:

nor2gate

port map (

i0 => nor2g3a,

i1 => nor2g3b,

bitout => in3

);

-- norg2:

-- nand4gate

-- port map (

-- i0 => din(2),

-- i1 => notws,

-- i2 => writeshift,

-- i3 => q3,

-- bitout => in2

-- );

norg2a:

nor2gate

port map (

i0 => din(2),

i1 => writeshift,

bitout => nor2g2a

);

norg2b:

nor2gate

port map (

i0 => notws,

i1 => q3,

bitout => nor2g2b

);

nor2gc:

nor2gate

port map (

i0 => nor2g2a,

i1 => nor2g2b,

bitout => in2

);

-- norg1:

-- nand4gate

-- port map (

-- i0 => din(1),

-- i1 => notws,

-- i2 => writeshift,

-- i3 => q2,

-- bitout => in1

-- );

norg1a:

nor2gate

port map (

i0 => din(1),

i1 => writeshift,

bitout => nor2g1a

);

norg1b:

nor2gate

port map (

i0 => notws,

i1 => q2,

bitout => nor2g1b

);

nor1gc:

nor2gate

port map (

i0 => nor2g1a,

i1 => nor2g1b,

bitout => in1

);

-- norg0:

-- nand4gate

-- port map (

-- i0 => din(0),

-- i1 => notws,

-- i2 => writeshift,

-- i3 => q1,

-- bitout => in0

-- );

norg0a:

nor2gate

port map (

i0 => din(0),

i1 => writeshift,

bitout => nor2g0a

);

norg0b:

nor2gate

port map (

i0 => notws,

i1 => q1,

bitout => nor2g0b

);

nor0gc:

nor2gate

port map (

i0 => nor2g0a,

i1 => nor2g0b,

bitout => in0

);

q(4) <= q4;

q(3) <= q3;

q(2) <= q2;

q(1) <= q1;

end architecture behavioral;

这给出了：

在q(0)上看到在A和B之间输出'0'，B和C a'1，C和D a'0'，D和E a'1'以及E和F a'1' ，之后是Din(4)的值的偏移，因为在ff4的din输入上没有多路复用器。

您会发现LSB首先出现。

重复实例化的组件通常可以成为使用generate语句的目标。

没有最小，完整和可验证的示例，我不得不猜测并决定对D_flipflop组件进行异步重置。