序列检测器(检测"10010序列")

IDLE为初始状态，A代表第一个状态"1"，B代表第二个状态"10",C代表第三个状态"100",D代表第四个状态"1001",E代表要输出的状态"10010"，G和F代表多余的状态分别为"1000"和"10001"。

module cy4( clk,rst_b,In,Y);
input clk,rst_b,In;
output Y;
reg[2:0]current_state,next_state;
wire Y;
parameter IDLE = 3'd0,//每个十进制数代表不同的状态
A = 3'd1,
B = 3'd2,
C = 3'd3,
D = 3'd4,
E = 3'd5,//输出为1的状态
F = 3'd6,
G = 3'd7;
assign Y = (next_state == D && In == 0)?1:0;
//状态为D时又收到了0，表明10010收到应有输出Y为高
always @(posedge clk or negedge rst_b)
if(!rst_b) current_state <= IDLE;
else current_state <= next_state;
always @(In,current_state)
case(current_state)
IDLE: if(In == 1) next_state <= A;
else next_state <= IDLE;
A: if(In == 0) next_state <= B;
else next_state <= A;
B: if(In == 0) next_state <= C;
else next_state <= F;
C: if(In == 1) next_state <= D;
else next_state <= G;
D: if(In == 0) next_state <= E;
else next_state <= A;
E: if(In == 0) next_state <= C;
else next_state <= A;
F: if(In == 0) next_state <= B;
else next_state <= A;
G: if(In == 0) next_state <= G;
else next_state <= F;
default:next_state <= IDLE;
endcase
endmodule

测试脚本代码：

`timescale 1 ns/ 1 ps
`define halfperiod 20
module cy4_vlg_tst();
reg clk;
reg rst_b;
reg[23:0]data;
wire Y,In;
assign In = data[23];
cy4 i1 (
.In(In),
.Y(Y),
.clk(clk),
.rst_b(rst_b)
);
initial
begin
clk=0;
rst_b=1;
#2 rst_b=0;
#30 rst_b=1;//复位信号
data=20'b1100_1001_0000_1001_0100;//码流数据
#(`halfperiod*1000)$stop;//运行500个时钟周期后停止仿真
end
always #(`halfperiod)clk = ~clk;//时钟信号
always @(posedge clk)
#2 data={data[22:0],data[23]};//移位输出码流
cy4 m(.In(In),.Y(Y),.clk(clk),.rst_b(rst_b));
//调用序列检测器模块
endmodule

时序仿真

总统设计思路：
1.列出检测器的逻辑功能
2.画出状态图，注意多余的状态图。
3.设计代码
4.写测试代码
5.时序仿真

最后

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