basys2数码管共阳还是共阴_FPGA笔记之基于BASYS 2开发板的数码管点亮 Label:Research...

教程：

https://wenku.baidu.com/view/3f9cf330aaea998fcc220e57.html

https://blog.csdn.net/ding_ding_fly/article/details/53458451

http://blog.chinaaet.com/dianzidebuguilu/p/5100050057

https://wenku.baidu.com/view/bdf8c8a09ec3d5bbfc0a7466.html

`timescale 1ns / 1ps

//

// Company:

// Engineer:

//

// Create Date: 16:56:08 12/07/2020

// Design Name:

// Module Name: sfsd

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//

module qiduanyimaqi(q_num, q_out);

input[3:0] q_num;

output[7:0] q_out;

reg[7:0] q_out;

always @(q_num) begin

case(q_num)

4'b0000:q_out = 8'b00000011;

4'b0001:q_out = 8'b10011111;

4'b0010:q_out = 8'b00100101;

4'b0011:q_out = 8'b00001101;

4'b0100:q_out = 8'b10011001;

4'b0101:q_out = 8'b01001001;

4'b0110:q_out = 8'b01000001;

4'b0111:q_out = 8'b00011011;

4'b1000:q_out = 8'b00000001;

4'b1001:q_out = 8'b00001001;

endcase

end

endmodule

module tsts1(A1,A2,A3,A4,B1,B2,B3,B4,led,F);

input A1,A2,A3,A4,B1,B2,B3,B4;

output [8:0] led;

output F;

reg [3:0] led_out;

reg [3:0] A;

reg [3:0] B;

//assign F=(A1*8+A2*4+A3*2+A4*1+B1*8+B2*4+B3*2+B4*1);

assign F=A1&B1;//

always @(*) begin

A={A1,A2,A3,A4};

B={B1,B2,B3,B4};

led_out=A+B;

end

assign led[0]=1;

assign led[1]=led_out[3];

assign led[2]=led_out[2];

assign led[3]=led_out[1];

assign led[4]=led_out[0];

assign led[5]=1;

assign led[6]=1;

assign led[7]=1;

assign led[8]=1;

endmodule

module dtsm(mclk, d1_wx, d1_out,A1,A2,A3,A4,B1,B2,B3,B4,led,F);

input mclk;

output[3:0] d1_wx;

output[7:0] d1_out;

reg[3:0] d1_wx = 4'b1110;

wire[7:0] d1_out;

reg[3:0] d_tmp_num;

reg clk_reg;

input A1,A2,A3,A4,B1,B2,B3,B4;

output [8:0] led;

output F;

reg [3:0] led_out;

reg [3:0] A;

reg [3:0] B;

reg [3:0] d_tmp_num1;

reg [3:0] d_tmp_num2;

reg [3:0] d_tmp_num3;

reg [3:0] d_tmp_num4;

reg [31:0] count_reg0;

reg [3:0] double1,double2;

//init

initial

begin

count_reg0=0;

d_tmp_num1=4'b0010;

d_tmp_num2=4'b0010;

d_tmp_num3=4'b0010;

d_tmp_num4=4'b0010;

end

assign led[0]=1;

assign led[1]=led_out[3];

assign led[2]=led_out[2];

assign led[3]=led_out[1];

assign led[4]=led_out[0];

assign led[5]=1;

assign led[6]=1;

assign led[7]=1;

assign led[8]=1;

//clk_flash

always@(posedge mclk)

if(count_reg0==32'd00050000)

begin

clk_reg<=~clk_reg;

count_reg0<=32'd0;

end

else

begin

count_reg0<=count_reg0+32'd1;

end

always @(*) begin

A={A1,A2,A3,A4};

B={B1,B2,B3,B4};

led_out=A+B;

if(led_out[0]!=1)begin

double1=4'b0000;

double2=led_out;

end

else begin

if(led_out[3]==1)begin

double1=4'b0000;

double2=led_out;

end

else begin

double1=1;

double2=led_out-4'b0010;

end

end

end

always @(posedge clk_reg) begin

case(d1_wx)

4'b1110:begin

d_tmp_num = B;//AN2

d1_wx = 4'b1101;

end

4'b1101:begin

d_tmp_num = d_tmp_num2;//AN1

d1_wx = 4'b1011;

end

4'b1011:begin

d_tmp_num = d_tmp_num1;//AN0

d1_wx = 4'b0111;

end

4'b0111:begin

d_tmp_num = A;//AN3

d1_wx = 4'b1110;

end

default: d1_wx = 4'b1110;

endcase

end

qiduanyimaqi qiduanyimaqi(d_tmp_num, d1_out);

endmodule