EDA 课堂练习2

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module count8(clk,count);
input clk;
output reg[7:0] count;
always@(posedge clk)
begin
count = count + 1;
end
endmodule

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function mul_4;  //默认返回1位reg 类型，如需返回其他类型，需要指明
input[1:0] ss;
inout s1,s2,s3,s4;
// 主体开始部分
begin
case(ss)
2'b00 : mul_4 = s1; /// 函数名就是函数的返回值
2'b01 : mul_4 = s2;
2'b10 : mul_4 = s3;
2'b11 : mul_4 = s4;
endcase
end
endfunction

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task mul_4;
intput[1:0] ss;
input s1,s2,s3,s4;
output out;
begin
case(ss)
2'b00 : out = s1; 
2'b01 : out = s2;
2'b10 : out = s3;
2'b11 : out = s4;
endcase
end
endtask

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module test(in,out);
input[7:0] in;
output reg[7:0] regout;
always@(in)
begin
if( ~in[7] )
out = in;
else
out = (~in+1) | 8'b10000000;
end
endmodule

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module (ina,inb,out);
input[3:0] ina,inb;
output reg[4:0] out;

function[3:0] abs
input[3:0] a;
begin
if ~ina[3]
abs = a;
else
abs = ~a + 1;
endfunction

always@(ina,inb)
begin
case({ina[3],inb[3]}
2'b00:out = abs(ina) - abs(inb);
2'b01:out = abs(ina) + abs(inb);
2'b10:out = -abs(ina) - abs(inb);
2'b11:out = -abs(ina) + abs(inb);
endcase
end
endmodule

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module test(in,out);
input[3:0] in;
output reg out;
always@(in)
begin
if (i>4)
out = 1;
else
out = 0;
end
endmodule