Verilog中使用连续@posedge会是什么现象，是否可综合
连续@posedge是可以综合，如果后面是阻塞赋值，会出现以下现象：这部分是源码中的执行部分：@(posedge clk) b = a;@(posedge clk) c = b;$display("blocking2 a = %b b = %b c = %b",a,b,c);@(posedge clk)begin c = b; b = a; $display("b...
