模100 计数器module counter100 #(parameter N=100, WIDTH=7)( input clk, input rst_n_a, output reg [WIDTH-1:0] counter, output reg en);always@(posedge clk or negedge rst_n_a) if(!rst_n_a) begin counter<=0; en<=0;end else if(counter==N-1) beg
verilog
2023-06-02
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