序列检测功能的时序电路(verilog 01110)
上代码：module timecheck(CLR,CLK,A,B,Z);input CLR,CLK,A,B;output Z;reg Z;wire [1:0]DATA_IN;reg [3:0]STATE;parameter state_idle = 4'b00x0, state_match1 = 4'b0000, state_match2 = 4'b0001, state...
