VHDL——JK触发器
1.管脚图2.真值表3.VHDL语言library ieee;use ieee.std_logic_1164.all;entity jkff is port(j,k,clk : in std_logic; q,nq : out std_logic);end jkff;architecture behave of jkff is signal q_s,nq_s : std_logic;begin process(clk,j,k) begin i
