上升沿下降沿检测电路verilog及RTL仿真
//检测上升沿电路//将原信号flag延迟一拍always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin flag_ff0<=0; end else begin flag_ff0<=flag; endendalways @(posedge c...
