我是靠谱客的博主 平常天空,最近开发中收集的这篇文章主要介绍verilog behavioral modeling--blocking and nonblocking,觉得挺不错的,现在分享给大家,希望可以做个参考。

概述

                                                                                             BLOCKING ASSIGNMENTS

1.A blocking procedural assignment statement shall be exectuted before the execution of the statements that follow it in a sequential block (我们一般都这样用)

2.A blocking procedural assignment statement shall not prevent the execution of statements that follow it in a parallel block(看来阻塞赋值不是永远阻塞后面的语句)

3.variable_lvalue = [delay_or_event_control] expression(variable_lvalue、delay_or_event_control 、expression 都有多种写法,可以参考IEEE标准)

    If variable_lvalue require an evaluation,it shall be evaluated at the time specified by the intra-assignment timing control.

    The = assignment operator used by blocking procedural assignments is also used by procedural continous assignments and continous assignments.

                                                                                             NONBLOCKING ASSIGNMENTS

1.the nonblocking procedural assignment allows assignment scheduling without blocking the procedural flow.

2.the nonblocking procedural assignment statement can be used whenever several variable assignments within the same time step can be made without regard to order or dependence upon each other.

3.variable_lvalue <=[delay_or_event_control] expression

   If variable_lvalue requires an evaluation,it shall be evaluated at the same time as the expression on the right-hand side.

   The order of evaluation of the variable_lvalue and the expression on the right-hand side is undefined if timing control is not specified.

 4.<=符合重载 : 小于等于 非阻塞赋值

 5.The nonblocking procedural assignments shall be evaluated in two steps .(跟time region有关)

       step1:the simulator evaluates the right-hand side of the nonblocking assignments and shedules the assignments for the end of the current time step

      step2:at the end of the current time step, the simulator updates the left-hand side of each nonblocking assignment statement

6.the order of the execution of distinct nonblocking assignments to a given variable shall be preserved. in other words ,if there is clear ordering of the execution of a set of nonbolcking assignments ,

  then the order of the resulting updates of the destination of the nonblocking assignments shall be the same as the ordering of the execution.(非阻塞也是可以写成阻塞的方式的)

         eg:

               module mutipe;

                   reg a;

                   initial a = 1;

                 //the assigned value of the reg is determinate

                   initial begin

                   a<= #4 0;

                  a<= # 1 ;

                  end

                   endmodule

7.If the simulator executes two procedural blocks concurrently and if these procedural blocks contain nonblocking assignment operators to the same variable, the final value of that variable is indeterminate.

          eg:

              module multipe2;

                 reg a;

                inital a =1;

               initial  a<= #4 0;   //schedules 0 at time 4

                initial a<= #4 1;  //schedules 1 at time 4

               //at time 4 ,a =??

              //the assigned value of  the reg is indeterminate

            endmodule

 

   8.always中可以blocking /nonblocking assignments

       initial 中可以blocking/nonblocking assignments

        似乎,我们一直关注的是always中组合逻辑用blocking,时序逻辑用nonblocking,initial中用blocking(此外系统函数必须放在initial 中)。

     其实,如果begin-end / fork-join 规定的串行/并行 跟 blocking / nonblocking 规定的阻塞/非阻塞交叉产生的效果。

转载于:https://www.cnblogs.com/chip/p/4073778.html

最后

以上就是平常天空为你收集整理的verilog behavioral modeling--blocking and nonblocking的全部内容,希望文章能够帮你解决verilog behavioral modeling--blocking and nonblocking所遇到的程序开发问题。

如果觉得靠谱客网站的内容还不错,欢迎将靠谱客网站推荐给程序员好友。

本图文内容来源于网友提供,作为学习参考使用,或来自网络收集整理,版权属于原作者所有。
点赞(43)

评论列表共有 0 条评论

立即
投稿
返回
顶部