FPGA---常用协议（uart协议：232、485）

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我是靠谱客的博主哭泣冷风，最近开发中收集的这篇文章主要介绍FPGA---常用协议（uart协议：232、485），觉得挺不错的，现在分享给大家，希望可以做个参考。

概述

232和485的区别在于一个全双工，一个半双工。

232可以一边读一边写，485要么读，要么写，通过一根使能信号来切换。

232接口：rx、tx。

485接口：rx、tx、en。

【范例1：rx】

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY myUART115200_rx IS
PORT (
bclk : IN std_logic; --clk=band*16
reset : IN std_logic;
rxd :in std_logic;
   rx_dout:out std_logic_vector(7 downto 0);
rx_ready :out std_logic

);
END myUART115200_rx;

ARCHITECTURE arch OF myUART115200_rx IS

constant s_idle : std_logic_vector(2 DOWNTO 0):="000";
constant s_sample : std_logic_vector(2 DOWNTO 0):="001";
constant s_wait : std_logic_vector(2 DOWNTO 0):="010";
constant s_shift : std_logic_vector(2 DOWNTO 0):="011";
constant s_stop : std_logic_vector(2 DOWNTO 0):="100";
constant Lframe : integer:=8;

SIGNAL state : std_logic_vector(2 downto 0);
SIGNAL cnt : integer range 0 to 2000;
SIGNAL dcnt : integer range 0 to 2000;
   SIGNAL num : integer range 0 to 8000;
SIGNAL data : std_logic_vector(7 downto 0);
   SIGNAL data1 : std_logic_vector(7 downto 0);
signal reg :std_logic;
signal z1:std_logic;
signal z2:std_logic;
signal z3:std_logic;
signal z4:std_logic;
signal zz:std_logic;

BEGIN
rx_dout<=data;
   rx_ready<=reg;
PROCESS(bclk,reset)
BEGIN
IF ( reset = '0') THEN
state<=s_idle ;
           cnt<=0;
           dcnt<=0;
           num<=0;
           data1<="00000000";
           reg<='0';
ELSIF(rising_edge(bclk))THEN
CASE state IS
               WHEN s_idle =>
                                               z1<=rxd;
                                               z2<=z1;
                                               z3<=z2;
                                               z4<=z3;
                                               reg<='0';
                                               zz<=(not z1)and (not z2) and (z3) and (z4);
                   if(zz='1')then state<=s_sample;
                   else state<=s_idle;
                   end if;

WHEN s_sample =>
if(num=1068)then data1(0)<=rxd;num<=num+1;
                                                           elsif(num=1936)then data1(1)<=rxd;num<=num+1;
                                                           elsif(num=2804)then data1(2)<=rxd;num<=num+1;
                                                           elsif(num=3672)then data1(3)<=rxd;num<=num+1;
                                                           elsif(num=4540)then data1(4)<=rxd;num<=num+1;
                                                           elsif(num=5408)then data1(5)<=rxd;num<=num+1;
                                                           elsif(num=6276)then data1(6)<=rxd;num<=num+1;
                                                           elsif(num=7144)then data1(7)<=rxd;num<=num+1;
                                                           elsif(num>7150)then state<=s_stop;data<=data1;num<=0;
                                                           else num<=num+1;
                                                           end if;

WHEN s_stop=>
                   if(num=20)then reg<='1';
                                           state<=s_idle;num<=0;
                                               else num<=num+1; state<=s_stop;
                                               end if;

when others=> state<=s_idle;
    reg<='0';

END CASE;
END IF;
END PROCESS;

END arch;

【范例2：tx】

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY myUART115200_tx IS
PORT (
bclk : IN std_logic; --clk=band*16
reset : IN std_logic;
tx_cmd       : IN std_logic;
tx_din            : IN std_logic_vector(7 DOWNTO 0);
tx_ready : OUT std_logic;
txd : OUT std_logic;
       ro:out std_logic
);
END myUART115200_tx;

ARCHITECTURE arch OF myUART115200_tx IS

constant s_idle : std_logic_vector(2 DOWNTO 0):="000";
constant s_start : std_logic_vector(2 DOWNTO 0):="001";
constant s_wait : std_logic_vector(2 DOWNTO 0):="010";
constant s_shift : std_logic_vector(2 DOWNTO 0):="011";
constant s_stop : std_logic_vector(2 DOWNTO 0):="100";
constant Lframe : integer:=8;

SIGNAL state : std_logic_vector(2 downto 0);
SIGNAL cnt : integer range 0 to 1024; --15
SIGNAL dcnt : integer range 0 to 1024; --15
SIGNAL txdt : std_logic;

BEGIN
txd <= txdt;
PROCESS(bclk,reset)
BEGIN
IF ( reset = '0') THEN
state<=s_idle ;
                   cnt<=0;
                   tx_ready<='0';
                   txdt<='1';
                   ro<='0';
ELSIF(rising_edge(bclk))THEN
CASE state IS

WHEN s_idle => tx_ready<='1';
                                                                       cnt<=0;
                                                                       txdt<='1';
                                                               if(tx_cmd='1')then state<=s_start;ro<='1';
                                                               else state<=s_idle;ro<='0';
                                                               end if;

       WHEN s_start =>
       tx_ready<='0';
                                   txdt<='0';
                                                               state<=s_wait;
WHEN s_wait=>
                        tx_ready<='0';
                                       if(cnt>=867)then cnt<=0;--14
                                       if(dcnt=Lframe)then state<=s_stop;
                                                                                                   dcnt<=0;
                                                                                                           txdt<='1';
                                                                       else state<=s_shift;
                                                                       txdt<=txdt;
                                                                       end if;
                                                               else state<=s_wait;
                                                   cnt<=cnt+1;
                                                               end if;

WHEN s_shift =>
               tx_ready<='0';
                                                               txdt<=tx_din(dcnt);
                                                               dcnt<=dcnt+1;
                                                               state<=s_wait;

WHEN s_stop=>
txdt<='1';
                               if(cnt>867)then --14
state<=s_idle;
                                                           cnt<=0;
                                                   tx_ready<='1';
                               else state<=s_stop;
                               cnt<=cnt+1;
                               end if;

when others=> state<=s_idle;

END CASE;
END IF;
END PROCESS;
END arch;