verilog 12-hour clock 可用代码

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    always @(posedge clk)begin
        if(reset)begin
            pm = 0;
        end
        else begin
            if(ena && ({hh, mm, ss} == 24'h115959))
                    pm = !pm;
            else
                pm = pm;
        end
    end
    second s (clk, reset, ena, ss);
    minute m (clk, reset, ss, ena, mm);
    hour h (clk, reset, ss, mm, ena, hh);
endmodule



module second (
    input clk,
    input reset,
    input enas,
    output [7:0] q);
    wire enass;
    assign enass = (enas && q[3:0] == 4'h9);
    
    modulo_10 counter10 (clk, reset, enas, q[3:0]);
    modulo_6 counter6 (clk, reset, enass, q[7:4]);
endmodule
        
module minute (
    input clk,
    input reset,
    input [7:0] s,
    input enam,
    output [7:0] q);
    wire x,enamm;
    always @(posedge clk) begin
        if(enam && s == 8'h58)
            x = 1;
    	else
            x = 0;
    end
    assign enamm = (x && q[3:0] == 4'h9);
    
    modulo_10 counter10 (clk, reset, x, q[3:0]);
    modulo_6 counter6 (clk, reset, enamm, q[7:4]);
endmodule        
 
module hour (     
    input clk,
    input reset,
    input [7:0] s,
    input [7:0] m,
    input enah,
    output [7:0] q);
    wire x;
    always @(posedge clk) begin
        if(enah && {m, s} == 16'h5958)
            x = 1;
        else
            x = 0;
    end
    modulo_12 counter (clk, reset, x, q);
endmodule
        
module modulo_6 (
    input clk,
    input reset,
    input slowena,
    output [3:0] q);

    always@(posedge clk)begin
        if(reset)
            q <= 0;
        else if(slowena)begin
            if (q == 5)//slowena is high
               	q <= 0;
	        	else
                q <= q + 1;
        end
        else
            q <= q;
    end
endmodule

module modulo_10 (
    input clk,
    input reset,
    input slowena,
    output [3:0] q);

    always @(posedge clk)begin
        if(reset)
            q <= 0;
        else if(slowena)begin
            if (q == 9)//slowena is high
               	q <= 0;
	        	else
                q <= q + 1;
        end
        else
            q <= q;
    end
endmodule
    
module modulo_12 (
    input clk,
    input reset,
    input slowena,
    output [7:0] q);
    always @(posedge clk)begin
        if(reset)
            q <= 8'h12;
        else if(slowena)begin
            case(q)
                8'h01:q = 8'h02;
                8'h02:q = 8'h03;
                8'h03:q = 8'h04;
                8'h04:q = 8'h05;
                8'h05:q = 8'h06;
                8'h06:q = 8'h07;
                8'h07:q = 8'h08;
                8'h08:q = 8'h09;
                8'h09:q = 8'h10;
                8'h10:q = 8'h11;
                8'h11:q = 8'h12;
                8'h12:q = 8'h01;
            endcase
        end
        else
            q = q;
    end
endmodule
                
            
                
                

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