Verilog刷题HDLBits——Count clock题目描述代码结果

81 阅读 0 评论 54 点赞

我是靠谱客的博主危机眼神，这篇文章主要介绍Verilog刷题HDLBits——Count clock题目描述代码结果，现在分享给大家，希望可以做个参考。

Verilog刷题HDLBits——Count clock

题目描述
代码
结果

题目描述

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
在这里插入图片描述

代码

复制代码

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    wire ena1,ena2,ena3,ena4,ena5;
    assign ena1 = ena&&ss[3:0]==4'd9;
    assign ena2 = ena1&&ss[7:4]==4'd5;
    assign ena3 = ena2&&mm[3:0]==4'd9;
    assign ena4 = ena3&&mm[7:4]==4'd5;
    assign ena5 = ena4&&hh=={4'b0001,4'b0001};
    count60 t_ss1(clk,reset,ena,4'b1001,ss[3:0]);
    count60 t_ss2(clk,reset,ena1,4'b0101,ss[7:4]);
    count60 t_mm1(clk,reset,ena2,4'b1001,mm[3:0]);
    count60 t_mm2(clk,reset,ena3,4'b0101,mm[7:4]);
    count12 t_hh(clk,reset,ena4,hh);
    count2 t_pm(clk,reset,ena5,pm);

endmodule

module count60 (input clk,reset,ena,input[3:0] cc,output[3:0] tt);
    always@(posedge clk)
        begin
            if(reset||(ena&&tt==cc))
               tt<=0;
            else
                if(ena)
                    tt<=tt+1'b1;
        end
endmodule

module count12 (input clk,reset,ena,output[7:0] tt);
    always@(posedge clk)
        begin
            if(reset) // 同步置12
                tt<={4'b0001,4'b0010};
            else
                begin
                    if(ena&&tt=={4'b0001,4'b0010}) // 12时变01
                        tt<={4'b0000,4'b0001};
                    else
                        begin
                            if(ena)
                                begin
                                    if(tt[3:0]==4'b1001)
                                        begin
                                            tt[3:0]<=4'b0000;
                                            tt[7:4]<=tt[7:4]+1'b1;
                                        end
                                    else
                                        tt[3:0]<=tt[3:0]+1'b1;
                                end
                        end
                end
        end
endmodule

module count2 (input clk,reset,ena,output pm);
    always@(posedge clk)
        begin
            if(reset||(ena&&pm==1))
                pm<=0;
            else
                if(ena)
                    pm<=pm+1;
        end
endmodule

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    wire ena1,ena2,ena3,ena4,ena5;
    assign ena1 = ena&&ss[3:0]==4'd9;
    assign ena2 = ena1&&ss[7:4]==4'd5;
    assign ena3 = ena2&&mm[3:0]==4'd9;
    assign ena4 = ena3&&mm[7:4]==4'd5;
    assign ena5 = ena4&&hh=={4'b0001,4'b0001};
    count60 t_ss1(clk,reset,ena,4'b1001,ss[3:0]);
    count60 t_ss2(clk,reset,ena1,4'b0101,ss[7:4]);
    count60 t_mm1(clk,reset,ena2,4'b1001,mm[3:0]);
    count60 t_mm2(clk,reset,ena3,4'b0101,mm[7:4]);
    count12 t_hh(clk,reset,ena4,hh);
    count2 t_pm(clk,reset,ena5,pm);

endmodule

module count60 (input clk,reset,ena,input[3:0] cc,output[3:0] tt);
    always@(posedge clk)
        begin
            if(reset||(ena&&tt==cc))
               tt<=0;
            else
                if(ena)
                    tt<=tt+1'b1;
        end
endmodule

module count12 (input clk,reset,ena,output[7:0] tt);
    always@(posedge clk)
        begin
            if(reset) // 同步置12
                tt<={4'b0001,4'b0010};
            else
                begin
                    if(ena&&tt=={4'b0001,4'b0010}) // 12时变01
                        tt<={4'b0000,4'b0001};
                    else
                        begin
                            if(ena)
                                begin
                                    if(tt[3:0]==4'b1001)
                                        begin
                                            tt[3:0]<=4'b0000;
                                            tt[7:4]<=tt[7:4]+1'b1;
                                        end
                                    else
                                        tt[3:0]<=tt[3:0]+1'b1;
                                end
                        end
                end
        end
endmodule

module count2 (input clk,reset,ena,output pm);
    always@(posedge clk)
        begin
            if(reset||(ena&&pm==1))
                pm<=0;
            else
                if(ena)
                    pm<=pm+1;
        end
endmodule