Verilog 刷题-Count clock

先附上代码 有空再补思路，自己写的很乱。

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    reg m0,m1,m2,h0,h1,h2,s0,s1,a1;
    assign s0 = (ss[3:0]==9)?1:0;
    assign s1 = (ss[7:4]==5&s0)?1:0;
    assign m0 = (ss[3:0]==9&ss[7:4]==5)?1:0;
    assign m1 = (m0&mm[3:0]==9)?1:0;
    assign m2 = (m0&mm[3:0]==9&mm[7:4]==5)?1:0;
    assign h0 = m2;
    assign h1 = (h0&hh[3:0]==9)?1:0;
    assign h2 = (h0&hh[7:4]==1&hh[3:0]==2)?1:0;
    assign a1 = (h0&hh[3:0]==1&hh[7:4]==1)?1:0;
    always@(posedge clk)begin
        if(reset==1)pm = 0;
        else if(a1==1)
            pm=~pm;
    end
 /*   bdcss s1(clk,reset,ena,[7:0]ss);
    bdcmm m2(clk,reset,ena,[7:0]mm);
    bdchh h3(clk,reset,ena,[7:0]hh);
*/
    always@(posedge clk)begin
        if(reset) ss[3:0]<=4'b0000;
        else if(ena==0) ss[3:0]<=ss[3:0];
        else if(s0)
            ss[3:0]<=4'b0000;
        else ss[3:0]<=ss[3:0]+8'b0001;
        end
    always@(posedge clk)begin
        if(reset) ss[7:4]<=4'b0000;
        else if(ena==0) ss[7:4]<=ss[7:4];
        else if(s1)
            ss[7:4]<=4'b0000;
        else if(s0)ss[7:4]<=ss[7:4]+8'b0001;
        end
    
    always@(posedge clk)begin
        if(reset) mm[3:0]<=4'b0000;
        else if(ena==0)mm[3:0]<=mm[3:0];
        else if(m1)
            mm[3:0]<=4'b0000;
        else if(m0) mm[3:0]<=mm[3:0]+8'b0001;
    end
     always@(posedge clk)begin
         if(reset) mm[7:4]<=4'b0000;
         else if(ena==0)mm[7:4]<=mm[7:4];
         else if(m2)
            mm[7:4]<=4'b0000;
         else if(m1) mm[7:4]<=mm[7:4]+8'b0001;
    end
    
    always@(posedge clk)begin
        if(reset) hh[3:0]<=4'b0010;
        else if(ena==0)hh[3:0]<=hh[3:0];
        else if(h1)
            hh[3:0]<=4'b0000;
        else if(h2) hh[3:0]<=4'b0001;
        else if(h0) hh[3:0]<=hh[3:0]+4'b0001;
    end
        always@(posedge clk)begin
            if(reset) hh[7:4]<=4'b0001;
            else if(ena==0)hh[7:4]<=hh[7:4];
            else if(h2)
                hh[7:4]<=4'b0000;
            else if(h1) hh[7:4]<=hh[7:4]+4'b0001;
    end
endmodule

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