概述
1.BCDadd100
参考HDLBits Day5 Bcdadd100变量下标中有变量的情况
注意大小端表示
步骤 注意整个工程大小端必须一致
1.定义的变量是大端还是小端模式
2.看升序（+：）还是降序（-：）
3.看位宽并进行转换
定义
reg [31:0] big_vect;
reg [0:31] little_vect;
解释
big_vect [0 +: 8] 从0 开始，升序，位宽为8 ======》》》》》big_vect [7 :0]
little_vect [0 +: 8] 从0 开始，升序，位宽为8 ======》》》》》little_vect [0 :7]
big_vect [15 -: 8] 从15开始，降序，位宽为8 ======》》》》》big_vect [15 :8]
little_vect [15 -: 8] 从15开始，降序，位宽为8 ======》》》》》little_vect [8:15]
注意verilog中语法不能 a[b-1:b+1]，a[high:low]中high、low不能为变量，因为位宽长度不确定，会报错Error (10734): Verilog HDL error at aa.v(8): i is not a constant。这里就类似于有一个基地址、数据长度，然后取数据。更加符合底层操作习惯。
2.Edgedetect
module edge_detect (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] in_reg
//将本次输入电平保存至in_reg
always@(posedge clk)begin
in_reg <= in;
end
//将本次输入电平和前一次的保存电平in_reg的反进行与操作，探测0 to 1的上升沿
always@(posedge clk)begin
pedge <= in&~in_reg;
end
//将本次输入电平的反和前一次的保存电平in_reg进行与操作，探测1 to 0的下降沿
//always@(posedge clk)begin
// pedge <= in&~in_reg;
//end
endmodule
3.Edgedetect2
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] in_reg;
#将本次输入电平保存至in_reg
always@(posedge clk)begin
in_reg <= in;
end
#将本次输入电平和前一次的保存电平in_reg的进行异或操作，探测上升沿或下降沿
always@(posedge clk)begin
anyedge <= in^in_reg;
end
endmodule
3.Edgecapture
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] in_reg;
always@(posedge clk)begin
in_reg <= in;
end
always@(posedge clk)begin
if(reset)
out <= 32'b0;
else
out <= ~in&in_reg | out; //锁存下降沿或保持原始输出
//out <= in&~in_reg | out; 则可以上升沿锁存或保持原始输出
end
endmodule
4.Dualedge
module top_module (
input clk,
input d,
output q
);
reg q_d1;
reg q_d2;
always@(posedge clk)begin
q_d1 <= d ^ q_d2;
end
always@(negedge clk)begin
q_d2 <= d ^ q_d1;
end
assign q = q_d1 ^ q_d2;
endmodule
当posedge clk触发时：
q_d1 变为 d ^ q_d2。因此 q = q_d1 ^ q_d2 = d ^ q_d2 ^ q_d2 = d。
当negedge clk触发时：
q_d2 变为 d ^ q_d1。因此 q = q_d1 ^ q_d2 = q_d1 ^ d ^ q_d1 = d。
日了狗了…边沿触发一个题都没做对…
5.ece241 2014 q7a
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = reset | ((Q == 4'd12) && enable == 1'b1);
assign c_d = c_load ? 4'd1 : 4'd0;
count4 u_counter (clk, c_enable, c_load, c_d, Q);
/*always@(posedge clk)
begin
if (reset)
Q <= 4'b0001;
else if(enable)
begin
if ( Q!=4'b1100)
Q <= Q + 4'b1;
else
Q <= 4'b0001;
end
end*/
endmodule
6.ece241 2014 q7b
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] one, ten, hundred;
assign c_enable = {(ten == 4'd9) && (one == 4'd9), (one == 4'd9), 1'd1 };
assign OneHertz = (hundred == 4'd9) && (ten == 4'd9) && (one == 4'd9);
bcdcount counter0 (clk, reset, c_enable[0], one);
bcdcount counter1 (clk, reset, c_enable[1], ten);
bcdcount counter2 (clk, reset, c_enable[2], hundred);
endmodule
7.Rule90
对位操作太不敏感
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
always @ (posedge clk)
begin
if (load)
q <= data;
else
begin
q <= {1'b0, q[511:1]} ^ {q[510:0] ,1'b0};
end
end
endmodule
8.Conwaylife
关键在于先padding，对初始数据进行padding，将16x16的矩阵扩展为18x18的矩阵
module top_module(
input clk,
input load,
input [255:0] data,
output [255:0] q );
reg [323:0] data_padding; //18*18
wire [255:0] q_next;
integer i,j,neighbour_cnt;
always @(*)
begin
//padding
data_padding[17:0] = {q[240],q[255:240],q[255]};
data_padding[323:306] = {q[0],q[15:0],q[15]};
for(i=1;i<17;i=i+1) begin
data_padding[i*18 +:18] = {q[(i-1)*16],q[(i-1)*16 +: 16],q[i*16-1]};
end
//count and update
for(i=0;i<16;i=i+1) begin
for(j=0;j<16;j=j+1) begin
neighbour_cnt = data_padding[(i+1)*18+j+1-1]+data_padding[(i+1)*18+j+1+1]+data_padding[i*18+j+1-1]+data_padding[i*18+j+1]+data_padding[i*18+j+1+1]+data_padding[(i+2)*18+j+1-1]+data_padding[(i+2)*18+j+1]+data_padding[(i+2)*18+j+1+1];
if(neighbour_cnt <= 1 | neighbour_cnt >=4)
q_next[i*16+j] = 0;
else if(neighbour_cnt == 3)
q_next[i*16+j] = 1;
else
q_next[i*16+j] = q[i*16+j]; //not change
end
end
end
always @(posedge clk)
begin
if(load)
q <= data;
else
q <= q_next;
end
endmodule
9.Fsm1s
没啥难的
关键是给的模板太诡异了，是一段式
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A = 0, B = 1;
reg present_state, next_state;
always @(posedge clk)
begin
if (reset)
present_state <= B;
else
present_state <= next_state;
end
always @(*)
begin
case(present_state)
B:begin
if (in ==1'b1)
next_state = B;
else
next_state = A;
end
A:begin
if (in == 1'b1)
next_state = A;
else
next_state = B;
end
endcase
end
assign out = (present_state == A)?0:1;
endmodule
10.Fsm3onehot
注意独热值的写法
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[C]&(~in) | state[A]&(~in);
assign next_state[B] = state[D]&in | state[A]&in | state[B]∈
assign next_state[C] = state[B]&(~in) | state[D]&(~in);
assign next_state[D] = state[C]∈
// Output logic:
assign out = state[D]? 1:0;
endmodule
11.ece241 2013 q4
解析看看https://www.cnblogs.com/guojingdeyuan/p/14669916.html
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
reg [1:0] current_state, next_state, last_state;
always @(posedge clk) begin
if(reset) begin
current_state <= S0;
last_state <= S0;
end
else begin
current_state <= next_state;
last_state <= current_state;
end
end
always @(*) begin
case(current_state)
S0 : begin
case(s)
3'b000 : next_state = S0;
3'b001 : next_state = S1;
3'b011 : next_state = S2;
3'b111 : next_state = S3;
default: next_state = S0;
endcase
end
S1 : begin
case(s)
3'b000 : next_state = S0;
3'b001 : next_state = S1;
3'b011 : next_state = S2;
3'b111 : next_state = S3;
default: next_state = S0;
endcase
end
S2 : begin
case(s)
3'b000 : next_state = S0;
3'b001 : next_state = S1;
3'b011 : next_state = S2;
3'b111 : next_state = S3;
default: next_state = S0;
endcase
end
S3 : begin
case(s)
3'b000 : next_state = S0;
3'b001 : next_state = S1;
3'b011 : next_state = S2;
3'b111 : next_state = S3;
default: next_state = S0;
endcase
end
default: next_state = S0;
endcase
end
always @(*) begin
case(current_state)
S0 : {fr3,fr2,fr1} = 3'b111;
S1 : {fr3,fr2,fr1} = 3'b011;
S2 : {fr3,fr2,fr1} = 3'b001;
S3 : {fr3,fr2,fr1} = 3'b000;
default: {fr3,fr2,fr1} = 3'b111;
endcase
end
//assign fr3 = (current_state == S0);
//assign fr2 = (current_state == S0) || (current_state == S1);
//assign fr1 = (current_state == S0) || (current_state == S1) || (current_state == S2);
always @(*) begin
if(current_state == S0)
dfr = 1'b1;
else if(last_state > current_state)
dfr = 1'b1;
else if(last_state < current_state)
dfr = 1'b0;
else
dfr = dfr; //will generate latch
end
endmodule
法二：
module top_module (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
// We have 6 states here.
parameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;
reg [2:0] state, next; // Make sure these are big enough to hold the state encodings.
// Edge-triggered always block (DFFs) for state flip-flops. Synchronous reset.
always @(posedge clk) begin
if (reset) state <= A2;
else state <= next;
end
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always@(*) begin
case (state)
A2: next = s[1] ? B1 : A2;
B1: next = s[2] ? C1 : (s[1] ? B1 : A2);
B2: next = s[2] ? C1 : (s[1] ? B2 : A2);
C1: next = s[3] ? D1 : (s[2] ? C1 : B2);
C2: next = s[3] ? D1 : (s[2] ? C2 : B2);
D1: next = s[3] ? D1 : C2;
default: next = 'x;
endcase
end
// Combinational output logic. In this problem, a procedural block (combinational always block)
// is more convenient. Be careful not to create a latch.
always@(*) begin
case (state)
A2: {fr3, fr2, fr1, dfr} = 4'b1111;
B1: {fr3, fr2, fr1, dfr} = 4'b0110;
B2: {fr3, fr2, fr1, dfr} = 4'b0111;
C1: {fr3, fr2, fr1, dfr} = 4'b0010;
C2: {fr3, fr2, fr1, dfr} = 4'b0011;
D1: {fr3, fr2, fr1, dfr} = 4'b0000;
default: {fr3, fr2, fr1, dfr} = 'x;
endcase
end
endmodule
隔了好久又开始刷题…
12.Fsm onehot
onehot的有限状态机
错误的写法：注意题干中说(The testbench will test with non-one hot inputs to make sure you’re not trying to do something more complicated).
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
parameter S0 = 10'b000_000_0001,S1 = 10'b000_000_0010,S2 = 10'b000_000_0100;
parameter S3 = 10'b000_000_1000,S4 = 10'b000_001_0000,S5 = 10'b000_010_0000;
parameter S6 = 10'b000_100_0000,S7 = 10'b001_000_0000,S8 = 10'b010_000_0000;
parameter S9 = 10'b100_000_0000;
always@(*)
begin
case(state)
S0: begin
if (in == 1)
next_state = S1;
else
next_state = S0;
end
S1: begin
if (in == 1)
next_state = S2;
else
next_state = S0;
end
S2: begin
if (in == 1)
next_state = S3;
else
next_state = S0;
end
S3: begin
if (in == 1)
next_state = S4;
else
next_state = S0;
end
S4: begin
if (in == 1)
next_state = S5;
else
next_state = S0;
end
S5: begin
if (in == 1)
next_state = S6;
else
next_state = S8;
end
S6: begin
if (in == 1)
next_state = S7;
else
next_state = S9;
end
S7: begin
if (in == 1)
next_state = S7;
else
next_state = S0;
end
S8: begin
if (in == 1)
next_state = S1;
else
next_state = S0;
end
S9: begin
if (in == 1)
next_state = S1;
else
next_state = S0;
end
default: next_state= 0;
endcase
end
assign out1 = ((&(~state[7:0]))&&(state[8])&&(~state[9])) || ((&(~state[8:0]))&&(state[9]));
assign out2 = ((&(~state[8:0]))&&(state[9])) || ((&(~state[6:0]))&&(state[7])&&(~state[9:8]));
endmodule
正确写法
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
parameter S0 = 0, S1 =1, S2 =2, S3 = 3, S4 = 4,
S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9;
assign next_state[S0] = (state[S0] & ~in) | state[S1] & (~in) |state[S2] & (~in) | state[S3] & (~in) |state[S4] & (~in)|state[S7] & (~in) | state[S8] & (~in)| state[S9] & (~in);
assign next_state[S1] = (state[S0] & in) | state[S8] & (in)|state[S9] & (in);
assign next_state[S2] = (state[S1] & in);
assign next_state[S3] = (state[S2] & in);
assign next_state[S4] = (state[S3] & in);
assign next_state[S5] = (state[S4] & in);
assign next_state[S6] = (state[S5] & in);
assign next_state[S7] = (state[S7] & in) | state[S6] & (in);
assign next_state[S8] = state[S5] & (~in);
assign next_state[S9] = state[S6] & (~in);
assign out1 = (state[S8] | state[S9]) ? 1:0;
assign out2 = (state[S9] | state[S7]) ? 1:0;
endmodule
最后
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