Exams/review2015 fsm

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );

    parameter S0=0,S1=1,S11=2,S110=3,S1101=4,Scounter=5,Sdone=6;
    reg [2:0] state,next_state;
    reg [1:0] shift_counter;
    
    always@(posedge clk) begin
        if(reset)
            state<=S0;
        else
            state<=next_state;
    end
    
    //shift_counter计数
    always@(posedge clk) begin
     	if(shift_ena) begin
            if(shift_counter==3)
                shift_counter<=0;
        	else
            	shift_counter<=shift_counter+1'b1;
        end
        else
            shift_counter<=0;
    end
    
    //Moore
    always@(*) begin
        case(state)
            S0: next_state = data?S1:S0;
            S1: next_state = data?S11:S0;
            S11: next_state = data?S11:S110;
            S110: next_state = data?S1101:S0;
            S1101: next_state = (shift_counter==3)?Scounter:S1101;
            Scounter: next_state = done_counting?Sdone:Scounter;
            Sdone: next_state = ack?S0:Sdone;
            default: next_state = S0;
        endcase
    end

    assign shift_ena=(state==S1101);
    assign counting=(state==Scounter);
    assign done=(state==Sdone);

endmodule

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