LATTICE DDR3 Design tips

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我是靠谱客的博主欢呼眼睛，最近开发中收集的这篇文章主要介绍LATTICE DDR3 Design tips，觉得挺不错的，现在分享给大家，希望可以做个参考。

概述

LATTICE DDR3 Design tips

1、Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?
For DDR3, the Address & Command outputs are generated using the DDR registers(ODDRXD1 modules). The DQSP and DQSN pins do not support DDR registers hence the error. These outputs will need to be assigned to non-DQS pins.Please see section “DDR3 Pinout Guidelines” in Technical Note TN1180 for all the DDR3 pinout rules.

2、Can the CLKP/CLKN outputs of the DDR3 memory controller be placed on the top side of the LatticeECP3 device?
The DDR3 (Double Data Rate - 3) CLKP/CLKN pads use a generic output DDR function (ODDR). The recommendation is to place the CLKP/CLKN outputs on the same side that the DQ and DQS pads are located. This is because the top side pads are not for the high-speed DDR function that can safely meet the DDR3 performance requirement on the LatticeECP3 device. Note that DDR3 DQ/DQS pads can be located only on the left or right side. Therefore, it is recommended that you locate the CLKP/CLKN pads on the left or right side depending on where the DQ/DQS pads are located.See TN1180 LatticeECP3 High-Speed I/O Interface, DDR3 Pinout Guidelines section for more general pinout guidelines.

3、Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?
During initializationThe DDR3 controller IP core performs both ZQ calibration long (ZQCL) and auto refresh commands during the DDR3 initialization process. It is a requirement defined by JEDEC DDR3 specification. After initializationAfter the initialization process is completed, the auto-refresh is still performed by the core at the interval configured with the tREFI parameter (Refresh interval time) and the number for the Auto-Refresh command burst (Auto Refresh Burst
Count). Therefore, there is no need for you to do anything for the auto refresh.
As for the ZQ calibration, it is an optional process for you to perform the calibration on demand basis. The DDR3 IP core does not provide auto-periodic ZQ calibration once the initialization process is completed. However, the core provides two user commands, ZQ_LNG (ZQ calibration long) and ZQ_SHRT (ZQ calibration short), to calibrate the DDR3 memory as needed. Since this process may impact the throughput and it is not a requirement once the initialization is completed, the ZQ calibration control will only run if implemented by the user.

4、Can I connect both the “mem_rst_n” and “rst_n” signals in the Lattice DDR3 IP core together to a system reset to meet the JEDEC initialization requirement?
The “rsn_n” signal resets both the DDR3 memory controller and the DDR3 memory devices while the “mem_rst_n” signal resets only the DDR3 memory devices. The JEDEC specification has two different cases of reset initialization. Power-up reset initialization: The memory reset needs to be asserted at least 200us with stable power. In this case, there is no need for the memory clock (CK) to be stable according to JEDEC. Since the DDR3 IP core does not provide a wait counter for this requirement, it is user’s responsibility to ensure to meet the required reset duration. 2. Reset assertion with stable power: Once the reset is asserted, according to JEDEC, it is required to remain below 0.2 * VDD for minimum 100ns. The Lattice DDR3 IP core supports this requirement. When you assert a reset pulse which is shorter than 100ns on mem_rst_n, the core will ensure it is asserted at least for 100ns.With these conditions, you can connect your system reset to both “rst_n” and “mem_rst_n” if your system reset duration is guaranteed longer than 200us after power becomes stable. If not, you will need to keep the mem_rst_n signal asserted at least for 200us with stable power to follow the JEDEC memory power-on reset requirement.

5、How can I configure the DDR3 memory clock to double the reference frequency (1:2:1 ratio) instead of multiple of 4x (1:4:2)?
The CSM (Clock Synchronization Module) module of the DDR3 memory controller ipcore multiplies the input reference clock frequency four times for the DDR3 bus operations and two times for the local bus operations. This means that the DDR3 IP core uses 1:4:2 ratio (input clock vs. DDR3 clock vs. local clock). If you use a DDR3 IP core version 1.2 or later (or any DDR3 PHY IP core version), you can manually change this ratio by following the steps below:
1. Open the ddr3_pll.v file inside the models folder using a text editor. It is located under ddr_p_evalmodelsecp3.
2. Launch IPexpress and select “PLL”. Configure the PLL with the options shown in the ddr3_pll.v file. Make sure you assign the module name to “ddr3_pll”.
3. Change the input and output clock frequencies to your desired values. If you want to use 150MHz as DDR3 reference clock input and DDR3 memory clock is 300MHz, you can set CLKOP=300.0MHz CLKOK=150.0MHz. Click “Calculate” then “Generate”.
4. If the generated PLL has more input or output pins than the original ddr_pll.v, you may need to manually edit the generated file so that the module can be properly instantiated. Use the original ddr3_pll.v file.
5. As an alternative, you can edit the original ddr_pll.v file with the divider values and parameters from the generated PLL module. You can select whichever way you feel more convenient.

6、I cannot assign the DDR3 memory clock (CK) pads to Bank 1 during the DDR3 core generation when the left side of a LatticeECP3 device is selected for a DDR3 interface running at 300MHz. How can I use the pins in Bank 1 for CK?
LatticeECP3 has the following pinout guideline for a DDR3 CK pair assignment (See TN1180 DDR3 Pinout Guidelines section.):
It’s recommended that the CK pads are located on the same side as data pads when the DDR3 bus is running at high speed (400MHz).
At a lower operating speed such as 333 or 300MHz, however, CK can be located on either the same side as data pads or a top-side bank. In this example, both Bank 0 and Bank 1 are legal locations to accommodate a CK pair if your target speed is 300MHz or 333MHz. The reason why the DDR3 IP core allows only Bank 0 in this case is because assigning the CK pad to Bank 1 is generally not practical in terms of pin resource allocation and static timing achievement. If the CK pads are located on the other side of the top bank, for example, it may cause a static timing failure if the internal routing delays are excessive. Although a pair in Bank 1 can be used as CK, the DDR3 IP core does not encourage you to use it due to this reason.
If you have to use a pair in Bank 1, you can generate a DDR3 IP core with CK assigned to Bank 0 first. Then, you can simply update the target bank for the CK pair from Bank 0 to Bank 1 in the preference file (.LPF) as shown below.
DEFINE PORT GROUP “EM_DDR_CLK_GRP” “em_ddr_clk_*” ;IOBUF GROUP “EM_DDR_CLK_GRP” IO_TYPE=SSTL15D BANK=1 ;
You will need to make sure not to violate the static timing requirement.

7、What should I do with the LatticeECP3 DDR3 memory interface VTT termination?
Only external VTT termination should be used for LatticeECP3 DDR3. Use of LatticeECP3’s internal on-die termination (ODT) is not recommended. According to the eye diagrams and simulation results from the Lattice factory tests, the recommended external resistor value is 100-120 ohms. It is encouraged that board designers perform the signal integrity simulations if possible for best resistor value in their environment. Below is a general termination guideline for LatticeECP3 DDR3 external VTT termination:
1. Placement of any external discrete resistors or resistor packs (RPACKS) is critical and must be placed within 0.6 inches of the LatticeECP3 ball.
2. 120 Ohm BGA RPACKS (CTS RT2432B7 type) are recommended for the 64- and 32-bit interfaces due to better routing and density issues. Each RPACK contains 18 resistors in a very small BGA footprint. Note that only 120, 75 and 50 ohm values are available in this package type.(http://www.ctscorp.com/components/Datasheets/ClearOneDDRSDRAMK.pdf) 3. 4x1 RPACKS (CTS 741X083101JP type) can also be used for the cases that 100 ohm value is needed without having routing/density issues. (http://www.ctscorp.com/components/Datasheets/CTSChipArrayDs.pdf)

8、Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?
Yes, you can. If you are using a Lattice DDR3 memory controller IP core version 1.2 or later, you can use a different rate of input reference clock. The original clock synchronization module (CSM) in the earlier version DDR3 IP cores require the fixed 1:2:4 ratio of clocks among the reference clock input (clk_in), system clock (sclk) and the DDR3 clock (eclk), respectively. The newer version CSM in the v1.2 or later supports variable clock ratios between the input reference clock and the system clock. The ratio between the system clock and the DDR3 clock must remain in 1:2 ratio.
If you use a 75MHz input reference clock for 400MHz DDR3 operations, for example, the supported clock ratio becomes 75MHz(clk_in) : 200MHz(sclk) : 400MHz(eclk).
Note that the CSM from the generated DDR3 IP core has the 1:2:4 ratio by default, and you will need to regenerate the PLL module to provide your desired clock ratio.

9、How can I terminate a DDR2 or DDR3 memory interface to VTT in LatticeECP3?
LatticeECP3 requires external termination to VTT for DDR1, DDR2 and DDR3 memory interface implementations. All DQ and DQS pins should be terminated to VTT using external termination resistors. The VTT level is 1/2 of VCCIO (0.9V for DDR2 and 0.75V for DDR3). SSTL (Stub Series Terminated Logic) I/O signaling requires parallel termination to VTT on the receiving end. While DDR2 memory has the ODT feature to fulfill this requirement for the write operations, the LatticeECP3 side should also have the termination for the read operations. The external termination resistors are used for this purpose. Note that LatticeECP2/M and LatticeXP2 use the same external termination scheme as LatticeECP3 for DDR1 and DDR2 memory interfaces.
It is suggested that you perform SI (signal integrity) simulation to obtain the best termination resistor value. If the SI simulation is not available, you can use the Lattice factory recommended values (75-ohm for DDR2 and 100- to 120-ohm for DDR3). A shorter trace length between a termination resistor to a LatticeECP3 ball is also crucial for better signal integrity results. Lattice recommends that you make a trace length between them no longer than 0.6”.
10、The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?
There are several alternatives that can be used to drive the LatticeECP3 DDR3 reference clock input:
1. Use an LVDS clock driver and connect directly to the DDR3-dedicated PLL input pair. LVDS25 is a compatible I/O type that can be used in a 1.5V VCCIO bank. This method provides you with the best signal integrity result.
2. You can internally drive the DDR3-dedicated PLL through the primary clock net. Choose an I/O bank of the device with an input level that is compatible with the clock driver you are using. Connect the clock driver to the PCLK (primary clock) input pad (or differential pair) of that bank. While the primary clock can add some amount of clock net jitter to the PLL, this method is still an acceptable solution that can be used as a secondary option. This option is also good for the single-ended clock driver.
3. Another option is to use a resistor-divider circuit that translates your clock driver output level to a compatible level of the 1.5V VCCIO bank. This method is useful when the clock driver is single-ended.

11、The generated DDR3 IP core includes a DDR3 DIMM (dual in-line memory module) instantiation module (ddr3_dimm_32.v) in the testbench when the selected memory type is On-board Memory. How can I instantiate the DDR3 device memory model in my testbench for simulation?
Although the file name includes “dimm”, the generated memory instantiation module such as “ddr3_dimm_32.v” is a memory wrapper that covers all DDR3 memory configurations including the On-board Memory type. This wrapper module includes all possible memory configurations and types including UDIMM, RDIMM, discrete memory with write leveling and address mirroring considerations . Therefore, it is okay for you to use this memory module for the simulation of any generated DDR3 IP core.If you do not want to use the memory wrapper file generated under the On-board Memory option, you can directly instantiate the memory model. You just need to make sure that the ddr3_parameters.vh file is properly included in the testbench. The memory model, ddr3.v, cannot be run without this parameter file.

12、Should I reset the Lattice DDR3 controller IP core after changing the “read_pulse_tap” signal?
The “read_pulse_tap” port is an input signal to the DDR3 controller IP core. Each DQS group has its own 3-bit read_pulse_tap port to control the READ signal timing to the DQSBUF hardware module. The DDR3 IP core allows dynamic READ pulse timing changes. Therefore, the value can be changed dynamically and there is no need to reset the DDR3 IP core.It is a good idea to change the read_pulse_tap value during the bus idling state instead of changing during DDR3 transactions to avoid any possible instantaneous data corruption. Please note that the read_pulse_tap signal is used as a static input in real applications although the IP core allows dynamic changes.

13、What is your recommendation to reduce or eliminate SSO noise related issues for DDR3 interface implementation using a LatticeECP3 device?
The following are the general SSO (simultaneous switching output) considerations and guidelines for DDR3 interface implementations:
Proper termination is needed to minimize SSO impacts. With sub-optimal termination, the SSO noise can be aggravated because the signal energy has no place to go but into the supply or ground plane. Follow the DDR3 termination guideline specified in TN1180.
Write leveling is the best way to decrease SSO. Make sure you turn on the Write Leveling option during the core generation if your application uses DDR3 DIMM. Write leveling will spread the read DQS/DQ arrival time to FPGA in time domain, which essentially spreads out noise and makes its peak noise level much lower.
Check your slew rate and drive strength settings. When you use slow slew and 8mA SSTL15 driving strength is 8mA, it would generate less amount of SSO compared to fast slew and 10mA.
Check the noise on VCCIO when the SSO noise is measured. If you see the same or similar pattern of noise on VCCIO, this could be a contributor to the noise. If you see the same noise, the pseudo powering will be helpful. Use of pseudo power pads helps noticeably decrease SSO. This would be an effective way to tame SSO noise. If you have unused I/O pads in the DDR3 banks, make them to be pseudo VCCIO and GND pads by connecting them to the VCCIO power and GND source on the PCB. Then set them to OUTPUT with driving High with maximum driving strength. You can set SSTL15 10mA output for them. They will provide more VCCIO power and stable grounding and decrease SSO noise. It is recommended more than 2/3 of pseudo power pads be connected to VCCIO.
Spread data DQS group pads as much as possible in a bank. If you have 7 DQS groups in a bank and want to implement a 32-bit DDR3, for example, having them assigned to “d,x,d,x,d,x,d” will have significantly lower SSO impact than a consecutive pad assignment like “x,x,d,d,d,d,x”. (where x: non-data DQS, d: data DQS)
If SSO noise on the address and control signals is concerned, use of series termination resistors on the address/command lines would help decrease SSO. 22-ohm or smaller value is recommended.
Isolating the address and command signals from the switching DQ signals to a different bank is also a good way to decrease SSO.
Probe measurement is also an important factor due to added noise from the ground loops and plane resonances. Make sure the ground lead of the probe is as short as possible, preferably less than 1/2 inch.
Well considered PCB layout is crucial to minimize the system’s SSO impact. Follow the generally known high-speed PCB implementation guidelines.

14、Which VREF pad should I use between VREF1 and VREF2 for a DDR2 or DDR3 memory controller?
Only VREF1 should be used for all DDR1, DDR2 and DDR3 memory controller applications. This is because only the VREF1 pad includes a dedicated circuit to detect preamble stages on the DQS signal coming from the memory device. It is important to know that you must not connect VREF1 to VREF2 together. It is because the detector circuit characteristics can be affected by the connected VREF2 pad when the VREF2 pad’s pull-up resister is turned on. Note that you can use VREF2 as a general I/O in DDR memory interface applications.

15、Why do I get the message “ERROR - map: IO buffer em_ddr_data_c_0 drives IO buffer em_ddr_data_pad_0 directly, but this is not possible” on most DDR3 interface signals after instantiation of a Lattice DDR3 IP core?
This FAQ is applicable to all Lattice DDR memory controller IP cores (DDR1/DDR2/DDR3/DDR3-PHY/LPDDR).
When a DDR memory interface signal uses a dedicated DDR I/O function, the DDR memory controller or PHY IP core netlist file (.ngo) includes an I/O buffer that is in conjunction with the required IOLOGIC block. Therefore, you must let the synthesis tool avoid automatic insertion of an additional I/O pad to the signal during the synthesis process. Otherwise, the synthesis tool infers an I/O pad to each of I/O port of your entire design. If the DDR3 interface signal gets the inferred I/O buffer, it will be conflicting with the one inside the netlist file, and this is why you got the error message.
Note that Lattice DDR3 controller/PHY IP core includes the I/O buffers on all DDR3 memory interface signals except the RESET# signal. Other DDR memory IP cores (DDR1/DDR2/LPDDR) include the I/O buffers only on the data (DQ) and data strobe (DQS) signals.
The user design that instantiates the IP core must follow the I/O pad handling configuration shown below:
Verilog:Use the provided black box core instantiation file ([core_name]_bb.v) found from the core root folder. This black box instantiation file includes the DDR3 signals that should not have additional I/O buffers shown below:
/* synthesis syn_black_box black_box_pad_pin=”em_ddr_data[31:0],em_ddr_dqs[3:0],em_ddr_clk[0:0],em_ddr_odt[0:0],em_ddr_cke[0:0],em_ddr_cs_n[0:0],em_ddr_addr[13:0],em_ddr_ba[2:0],em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n” */; //DDR3 32-bit IP core example
/* synthesis syn_black_box black_box_pad_pin=”em_ddr_data[31:0],em_ddr_dqs[3:0]” */; //DDR2 32-bit IP core example
VHDL:Your VHDL design that instantiates the DDR3 core following attribute declaration:
attribute black_box_pad_pin : string;attribute black_box_pad_pin of ddr3core : component is “em_ddr_data(15:0), em_ddr_dqs(1:0),em_ddr_clk(0:0),em_ddr_odt(0:0),em_ddr_cke(0:0),em_ddr_cs_n(0:0),em_ddr_addr(12:0),em_ddr_ba(2:0),em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n” ; – DDR3 16-bit example
attribute black_box_pad_pin : string;attribute black_box_pad_pin of ddr3core : component is “em_ddr_data(31:0),em_ddr_dqs(3:0)”; – DDR2 32-bit example
The wrapper file (ddr_sdram_mem_top_wrapper.vhd) in the generated core, is a good reference to follow.

16、How do I place DDR3 interface pins to minimize SSO impact?
1. Try using the DQS groups in the middle of the (right or left) edge if the DDR3 data width does not require to use the whole edge of LatticeECP3. Avoid the corner DQS groups if possible.
2. Locate a spacer DQS group between two adjacent data DQS groups if possible. A DQS group becomes a spacer DQS group if the I/O pads inside the group are not used as data pads (DQ, DQS, DM). The pads in a spacer group can be used for address, command, control or CK pads as well as for user logic or the pseudo power pads.
3. It is recommended that you locate four or more pseudo VCCIO/ground (GND) pads inside a spacer DQS group. An I/O pad becomes a pseudo power pad when it is configured to OUTPUT with its maximum driving strength (SSTL15, 10mA) and connected to the external VCCIO or ground power source on the PCB. Your design needs to drive the pseudo power I/O pads according to the external connection. (i.e., you assign them as OUTPUT and let your design drive “1” for pseudo VCCIO pads and “0” for pseudo GND pads in your RTL coding.) The recommended four pads are two pads in both ends (the first and the last ones in the group) and two DQS (positive and negative) pads in the middle.
4. You may have one remaining pad in a data DQS group which is not assigned as a data pad in a DDR3 interface. Assign it to pseudo VCCIO or pseudo GND. Preferred location is in the middle of the group (right beside DQS pads). Note that you will not have this extra pad if the DQS group includes a VREF1 pad for the bank.
5. Assign the DM (data mask) pad in a data DQS group close to the other side of DQS pads where a pseudo power pad is located. If the data DQS group includes VREF1, locate DM to the other side of VREF1 with respect to DQS. It can be used as an isolator due to its almost static nature in most applications.
6. Other DQS groups (neither data nor spacer group) can be used for accommodating DDR3 address, command, control and clock pads. It is recommended that you assign all or most DQS pads (positive and negative) in these groups to pseudo power. Since LatticeECP3 DQS pads have a dedicated DDR function that cannot be shared with other DDR3 signals, they are good pseudo power pad candidates.
7. You can assign all unused I/O pads to pseudo power if you do not have a plan to use them in the future. Assigning more I/O pads to VCCIO is desirable because LatticeECP3 has four VCCIO pads in each bank while more GND pads are available. Keep the total pseudo power pad ratio (VCCIO vs. GND) between 2:1 to 3:1.
8. Although it is not significantly necessary, it would be slightly more effective if you locate a pseudo VCCIO to a positive pad (A) and GND to a negative pad (B) of a PIO pair if possible.
9. If a bank includes unused input-only pads such as dedicated PLL input pads, connect them to VCCIO on your PCB. They can also be used as isolators and the connections on the board should provide good shielding. No extra consideration is necessary in your design.
10. It is a good idea to shield the VREF1 pad by locating pseudo power pads around it if the VREF1 pad is not located in a data DQS group.
11. Avoid fast switching signals being located close to the XRES pad. XRES requires an external resistor which is used to create the bias currents for the IO. Since this resistor is used for a calibration reference for sensitive on-chip circuitry, careful pin assignment around the XRES pad is also necessary to produce less jittery PLL outputs for DDR3 operations.
See TN1180 LatticeECP3 High-Speed I/O Interface, DDR3 Pinout Guidelines section for more general pinout guidelines along with these SSO guidelines.

17、What is the maximum DDR3 device loading that can be driven by the Lattice DDR3 controller IP core?
Both the data and address/command bus loading factors should be considered to answer the question.
The Lattice DDR3 controller and DDR3 PHY IP cores were validated to allow up to two-DDR3 data pin loading on the DQ, DQS and DM signals at the rate of 400MHz/800Mbps using a LatticeECP3 device. This means that the IP cores support up to two-rank (or two-chip selects) memory configurations. If your application is DDR3 DIMM(dual in-line memory module) based, you can use a single- or dual-rank DIMM module. Use of two separate single-rank modules is not recommended because the core’s DDR3 ODT (on-die termination) control is optimized for a single DIMM configuration.
As for the address/command bus, you can drive up to 16-device loading on each address, command or control pad. 16-device loading is typical for a dual-rank DIMM. We recommend you use the 2T option when a dual-rank DIMM is used to provide the better setup and hold timing window. The 2T option is available when you generate a DDR3 core targeting a dual-rank DDR3 DIMM memory configuration.

18、Why does my regenerated DDR3 IP core have different CL and CWL values from the original LPC file that has CL=7 and CWL=6 at 400MHz?
The reason why you see the different CL (CAS Latency) and CWL (CAS Write Latency) values after core regeneration is because the IPexpress DDR3 GUI script performs the JEDEC compatibility check. The original LPC that you used contains an illegal setting which is CL=7 and CWL=6 at 400MHz. The GUI script changed them back to default due to the violated setting.
You see this regulated core regeneration if you are using a DDR3 IP core version 1.3 or earlier. To support special DDR3 applications that require to run at out-of-JEDEC compatibility ranges, the future DDR3 core releases will not perform the JEDEC compatibility check during the core regeneration.
To workaround this issue using the DDR3 v1.3 or earlier, you will need to manually set CL/CWL in the GUI when the core is regenerated.

19、Why do I have an error during the mapping of a DDR3 IP-based design, saying “Error: Output buffer drives output buffer: each IO pad requires one and only one buffer…”?
This map error is caused by the duplicated IO buffers which are located both inside the IP core netlist file (.ngo) and your top-level code that instantiates the IP core netlist. DDR3 IP cores already include all the IO buffers for the DDR3 bus signals inside the ngo file. Therefore, you must disable the IO buffer insertion during the synthesis of your top-level module. You can do this by telling the synthesis tool not to insert any IO buffer to those signals.
The following attribute should be implemented in your Verilog or VHDL top.
black_box_pad_pin
This tells the synthesis tool that the IO pads are already included in the black box (DDR3 core nelist) so that the top-level does not instantiate the additional IO buffers. See the following examples (The core name is “ddr3core” in this example.):
VHDL:
attribute syn_black_box : string; attribute syn_black_box of ddr3core : component is true; attribute black_box_pad_pin : string; attribute black_box_pad_pin of ddr3core : component is “em_ddr_data(31:0),em_ddr_dqs(3:0),em_ddr_clk(0:0),em_ddr_odt(0:0),em_ddr_cke(0:0),em_ddr_cs_n(0:0),em_ddr_addr(13:0),em_ddr_ba(2:0),em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n” ;
Verilog:
Add the following synthesis directive to the module definition (see a IP core Verilog header file for the complete structure):
/* synthesis syn_black_box black_box_pad_pin=”em_ddr_data[63:0],em_ddr_dqs[7:0],em_ddr_clk[0:0],em_ddr_odt[0:0],em_ddr_cke[0:0],em_ddr_cs_n[0:0],em_ddr_addr[27:0],em_ddr_ba[2:0],em_ddr_ras_n,em_ddr_cas_n,em_ddr_we_n” */;

20、Some of the DDR3 IP core preferences are being ignored in my design, and I am getting a few timing errors. How can this happen?
There are two possibilities:
1. The signal paths in the ignored preferences may not be correct. This usually happens when a user takes the IP core preferences as-is without getting them localized. If there is any added hierarchy, the paths in the original preferences must be updated. For example, let’s assume that you have the following form preference generated from IPexpress:
LOCATE PGROUP “clocking/clk_phase/phase_ff_0_inst/clk_phase0” SITE “R32C5D” ;
If there is any hierarchy change, for example another top-level instantiates the core with the name “ddr3”, the preference must be updated accordingly as shown below:
LOCATE PGROUP “ddr3/clocking/clk_phase/phase_ff_0_inst/clk_phase0” SITE “R32C5D” ;u201D
See “Handling DDR3 IP Preferences in User Designs” section in the IP user guide, IPUG80.PDF.
2. The target device may have been changed. If this is the case, a new DDR3 core with the same configuration needs to be regenerated targeting the new device. This is to get the new preference set for the new target device. The location for the example preference varies depending not only on the device but also on the package size. Once you generate a core targeting a right device, you will get the corresponding locations from the generated core LPF. Make sure the DQS pin locations also get updated. Once the new preferences are obtained, their paths can be localized as explained in the #1 case above.

21、Where can I get the maximum skew data between the DDR3 CK and address/command pads in LatticeECP3?
In DDR memory interfaces, the CK rising edge is located ideally right in the middle of the address and command eyes to maximize the tIS and tIH margin. LatticeECP3 allows this by generating the CK and the address/command signals from the same phase clocks (2x and 1x, respectively) then inverting the CK output phase. Since the CK and
address/command generations use the dedicated DDR IO blocks, there is nooutstanding data-path skew difference between them. However, there is aclock skew difference between them and the difference is clearly listedin the datasheet. Since both CK and the address/command signals are driven by the primary clocks from the same PLL, take the maximum primary clock net skew data to determine the worst case window from the datasheet.
See the “LatticeECP3 External Switching Characteristics” table in the LatticeECP3 datasheet. Find your device and apply the number for the following cases:
1. tSKEW_PRIB: take this if DDR3 address/commands and CK are inside the same bank2. tSKEW_PRI: take this if DDR3 address/commands and CK are located in different banks
Note that the numbers in the table include both the clock distribution skew and IO pad skew.

22、Can I connect an external Low Voltage Differential Signal 2.5V (LVDS25) clock output to a LatticeECP3 DDR3 bank which is 1.5V VCCIO bank?
Yes, you can drive an external Low Voltage Differential Signal (LVDS) clock generator to an input pair of LatticeECP3 1.5V VCCIO bank. Although LatticeECP3 LVDS25 is characterized in 2.5V and 3.3V, you can safely use an external LVDS25 driver to drive LatticeECP3 1.5V input pads. The input of the left and right edges of LatticeECP3 has a PCI clamp circuit that clamps the input voltage at VCCIO + 0.3V. This allows you to use LVDS input up to 1.8V with the common mode voltage up to 1.75V. This provides enough DC signaling margin to the standard LVDS drivers. There is no problem in implementing in the software because the LVDS25 IO type is a compatible type to an 1.5V VCCIO bank. SSTL15D can also be used to get an external LVDS25 input.

23、How do I implement differential SSTL pads in software for my DDR memory interface design?
Differential SSTL (Stub Series Terminated Logic) I/O type is specified using a Place and Route (PAR) preference called “IOBUF”. You only need to specify the positive-end of the differential SSTL pair in your RTL design. The differential I/O appears, in your RTL, like any other single ended I/O. The software automatically assigns the negative-end pads by using IO_TYPE=SSTL18D_II (SSTL25D_II for DDR1, SSTL15D for DDR3) attribute in combination with the IOBUF preference to implement differential SSTL type. See the following example:
In RTL:(Verilog) output em_ddr_clk; inout em_ddr_dqs; (VHDL)em_ddr_clk out std_logic;em_ddr_dqs inout std_logic;
In the preference file (.lpf): LOCATE COMP “em_ddr_clk” SITE “U2”; IOBUF PORT “em_ddr_clk” IO_TYPE=SSTL18D_II; LOCATE COMP “em_ddr_dqs” SITE “AM6”; IOBUF PORT “em_ddr_dqs” IO_TYPE=SSTL18D_II;
After the design has the logic mapped and placed, the pad report file (.pad) will show the positive and negative pin assignment:| U2/6 | em_ddr_clk+ | SSTL18D_II_OUT | PL62A | LDQ67 | | U1/6 | em_ddr_clk- | SSTL18D_II_OUT | PL62B | LDQ67 | | AM6/6 | em_ddr_dqs+ | SSTL18D_II_BIDI | PL121A | LDQS121 | | AN6/6 | em_ddr_dqs- | SSTL18D_II_BIDI | PL121B | LDQ121 |

24、How do I implement multiple DDR2/3 memory interfaces in one side of LatticeECP3 when there is only one DQSDLL available per side?
LatticeECP3 devices have one DQSDLL per side. DQSDLL has an input port called UDDCNTLN that allows its DLL code value (DQSDEL output) to be updated while it is asserted Low. The updated code value is used to generate precise PVT (Process Voltage Temperature) compensated delays for DDR write and read operations while UDDCNTLN is deasserted High. The memory controller must properly control UDDCNTLN to take advantage of PVT compensated DDR write and read operations. UDDCNTLN must go active only while the memory controller is not performing any DDR read or write operations in order to avoid data corruption that may be caused by dynamic changes of DLL code. When multiple DDR3 memory interfaces are implemented in either the left or the right side, the DQSDLL in the same side must be shared so that all controllers can utilize the PVT compensation.If your DDR2/3 memory controller has an active-Low DLL update control output signal and you want to implement N number of memory controller in the same side, each memory controller output can be connected to a N-input OR gate input and the OR gate output is connected to the UDDCNTLN input of the DQSDLL.If your DDR2/3 memory controller has an active-High DLL update control output signal and you want to implement N number of memory controller in the same side, each memory controller output can be connected to a N-input NAND gate input and the NAND gate output is connected to the UDDCNTLN input of the DQSDLL.

25、Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?
DDR (Double Data Rate) memory interfaces use SSTL signaling which requires parallel termination to VTT at the receiver side. The external VTT termination on data is for the memory controller side during the read operations. Since the address, command and control signals are output from the memory controller, VTT termination is not required at the controller side. Therefore, the address, command and control signals need to be terminated to VTT at the memory side because the DDR2/3 memory is the receiver for these signals.It is required that the external termination resistors on the data signals are located as close to the ECP3 pins as possible with not longer than 600-mil (0.6”) trace length. We recommend you run signal integrity (SI) Simulation to determine the best termination value. If SI simulation is not available, parallel termination of 100~120 ohms to VTT for DDR3 (75 ohms for DDR2) is recommended.

26、Can I use all availabe DQS pad in a Lattice FPGA device for my DDR1/2/3 memory controller applications?
It depends on your memory controller application. Some DQS pad groups may not provide enough number of associated DQ pads because some DQ pads may not be bonded out. Although not many DQS groups have difference DQ sizes, you should pay careful attention to choose a DQS pin and check if the all associated DQ pads for the selected DQS group are enough to meet your application need.
The decision will usually depend on whether your memory controller uses eight DQ pads or four per DQS. While majority DDR memory applications require eight DQ pads per DQS, there are some others like a RDIMM memory controller that uses only four DQ pads per DQS.To know how many DQ pads you need per DQS for eight DQ per DQS, use the following guideline:Minimum number of DDR1 DQS group pads:DQS (1) + DQ (8) + DM (1) = 10 padsMinimum number of DDR2 DQS group pads:DQS (1) + DQ (8) + DM (1) = 10 pads (single ended DQS)DQS (2) + DQ (8) + DM (1) = 11 pads (differential DQS)Minimum number of DDR3 DQS group pads:DQS (2) + DQ (8) + DM (1) = 11 pads (differential DQS)Note:1. This guideline considers DM as a mandatory signal. If DM is not required, you can subtract one from the minimum required size.2. If a DQS group includes a VREF1 pad for the bank, you have to count one additional DQ/VREF1 dual function pad.