xilinx Ultrascale 四核A53+双核R5+GPU+fpga 平台初识

一、boot启动：

1.硬件资源：

64KB rom 用于完成以下工作：
Pre-boot tasks
　　° Clean PMU RAM
　　° Enable the System Monitor and check LP domain supply.
　　° Configure PLLs with initial settings.
　　° Trigger and sequence the necessary scan and BIST clear of PS.
　　° Release reset to CSU.
　　° Communicate error, if required. At boot, the only error communication is through the PS_ERROR_OUT register, and then the error codes can be read by JTAG.
Post-boot tasks
　　° Power-up and power-down domains within the PS.
　　° Enable and control BISR.
　　° Reset blocks when requested or as a part of the master power-ups.
Execute firmware codes upon request.

xx RAM,可以运行用户程序实现电源管理，在PMU上运行用户程序的步骤如下:

• Application program on another processor executes IPI0 to the PMU.
• IPI0 interrupt service routine.
　　° Disables all interrupts.
　　° Executes a sleep instruction. The instruction after the sleep instruction must be a branch to the address for the user code in RAM.
• The application program loads the PMU user program into the RAM.
• The application program writes a 1 to bit [0] of the PMU global control register to wake up the processor.
• PMU starts executing instructions following the sleep instruction and returns to the main() function in the code.
• PMU branches to the user code.
• The user code clears the bit [0] in the PMU global control register and enables the interrupt.

二、框架结构：

平台管理单元PMU是对几个处理器和fpga进行统一管理的Prosser 。它的gpio会与PL和PS相连，GPI/O0[31:0]自用；GPI/O1[31:0],GPI/O2[31:0]用于和PS通信；GPI/O3[31:0]用于和PL通信，（输入32+输出32） × 4组  = 共计256个 。具体每个管脚干什么用见 ug1058 p117页。

MIO[31:26] are allocated to the PMU GPI and are routed to PMU GPI1[15:10]. MIO[37:32]
are allocated to the PMU GPO and are driven by PMU GPO1[5:0]. Among the five GPOs,
PMU ROM uses MIO[32] and MIO[33] to signal requests to power up the V CC_PSINTFP and
V CCINT supplies, respectively. By default, the MIO[32] and MIO[33] are considered (by the
ROM) to be the interface to the FPD and PLD power supplies, respectively