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module adder(
input clk,
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] c
);

always@(posedge clk)
    c<=a+b;

endmodule

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module suber(
input wire clk,
input wire [31:0]  a,
input wire [31:0]  b,
output reg [31:0] c
);
always@(posedge clk)
    c<=a-b;
endmodule

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module alu (
input wire clk,
input wire mode,
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] out
);

wire [31:0] c1;
wire [31:0] c2;

assign out=(mode==1)?c1:c2;             //mode==1,add,mode==0,sub

adder U1(
.clk(clk),
.a(a),
.b(b),
.c(c1)
);

suber U2(
.clk(clk),
.a(a),
.b(b),
.c(c2)
);
    
endmodule

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module test;

reg clk;
reg [31:0] a;
reg [31:0] b;
wire [31:0] out;
reg mode;
//
initial begin
    clk=0;
    forever begin
        #5 clk=~clk;
    end
end
//
always@(posedge clk)
    mode<=$random%2;

always@(posedge clk)
begin
    a<=$random%128+128;
    b<=$random%128+128;
end

initial
begin
    #1000
    $stop;
end

alu U(.clk(clk),
      .mode(mode),
      .a(a),
      .b(b),
      .out(out));

initial begin
   $fsdbDumpfile("./alu.fsdb");
   $fsdbDumpvars(0);
end

endmodule

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initial begin
   $fsdbDumpfile("./alu.fsdb");
   $fsdbDumpvars(0);
end

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vcs -full64 -f filelist.f -timescale=1ns/1ns -sverilog -debug_access -kdb -lca -R -l ./output.log

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verdi -sv -f -Uart_rtl.f -ssf alu.fsdb