(筆記) 如何設計5位元的8對1多工器? (SOC) (Verilog) (MegaCore)

72 阅读 0 评论 48 点赞

我是靠谱客的博主安静蜗牛，最近开发中收集的这篇文章主要介绍(筆記) 如何設計5位元的8對1多工器? (SOC) (Verilog) (MegaCore)，觉得挺不错的，现在分享给大家，希望可以做个参考。

概述

Abstract
基本的8對1多工器，使用Verilog與megafunction實現。

Introduction
使用環境：Quartus II 7.2 SP3 + ModelSim-Altera 6.1g + DE2(Cyclone II EP2C35F672C6)

Method 1：
自己撰寫Verilog

mux_5_8_1v2.v / Verilog
使用continuos assignment

1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename    : mux_5_8_1_v2
5 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
6 Description : Demo how to write 8 to 1 MUX
7 Release     : 07/10/2008 1.0
8 */
9
10 module mux_5_8_1_v2 (
11 input [ 4 : 0 ] a,
12 input [ 4 : 0 ] b,
13 input [ 4 : 0 ] c,
14 input [ 4 : 0 ] d,
15 input [ 4 : 0 ] e,
16 input [ 4 : 0 ] f,
17 input [ 4 : 0 ] g,
18 input [ 4 : 0 ] h,
19 input [ 2 : 0 ] sel,
20 output [ 4 : 0 ] y
21 );
22
23 assign y = (sel == 3 ' b000) ? a :
24            (sel == 3 ' b001) ? b :
25            (sel == 3 ' b010) ? c :
26            (sel == 3 ' b011) ? d :
27            (sel == 3 ' b100) ? e :
28            (sel == 3 ' b101) ? f :
29            (sel == 3 ' b110) ? g : h;
30
31 endmodule

mux_5_8_1_v3.v / Verilog
使用always block

1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename    : mux_5_8_1_v3
5 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
6 Description : Demo how to write 8 to 1 MUX
7 Release     : 07/10/2008 1.0
8 */
9 module mux_5_8_1_v3 (
10 input [ 4 : 0 ] a,
11 input [ 4 : 0 ] b,
12 input [ 4 : 0 ] c,
13 input [ 4 : 0 ] d,
14 input [ 4 : 0 ] e,
15 input [ 4 : 0 ] f,
16 input [ 4 : 0 ] g,
17 input [ 4 : 0 ] h,
18 input [ 2 : 0 ] sel,
19 output reg [ 4 : 0 ] y
20 );
21
22 always@(a or b or c or d or e or f or g or h or sel) begin
23 case (sel)
24     3 ' b000: y = a;
25     3 ' b001: y = b;
26     3 ' b010: y = c;
27     3 ' b011: y = d;
28     3 ' b100: y = e;
29     3 ' b101: y = f;
30     3 ' b110: y = g;
31     3 ' b111: y = h;
32 endcase
33 end
34
35 endmodule

Method 2：
使用Megafunction：lpm_mux

mux_5_8_1

mux00

mux_5_8_1_v.v / Verilog

1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename    : mux_5_8_1_v.v
5 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
6 Description : Demo how to write 8 to 1 MUX by megafunctions
7 Release     : 07/10/2008 1.0
8 */
9 module mux_5_8_1_v (
10 input [ 4 : 0 ] a,
11 input [ 4 : 0 ] b,
12 input [ 4 : 0 ] c,
13 input [ 4 : 0 ] d,
14 input [ 4 : 0 ] e,
15 input [ 4 : 0 ] f,
16 input [ 4 : 0 ] g,
17 input [ 4 : 0 ] h,
18 input [ 2 : 0 ] sel,
19 output [ 4 : 0 ] y
20 );
21
22 wire [ 39 : 0 ] i = {h, g, f, e, d, c, b, a};
23
24 lpm_mux # (.lpm_width( 5 ), .lpm_widths( 3 ), .lpm_size( 8 ))
25 u0 (
26 .data(i),
27 .sel(sel),
28 .result(y)
29 );
30
31 /*
32 lpm_mux u0 (
33 .data(i),
34 .sel(sel),
35 .result(y)
36 );
37
38 defparam u0.lpm_width = 5;
39 defparam u0.lpm_widths = 3;
40 defparam u0.lpm_size   = 8;
41 */
42
43 endmodule

Testbench
mux_5_8_1_v_tb.v / Verilog

1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename    : mux_5_8_1_v_tb.v
5 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
6 Description : Demo how to write 8 to 1 MUX testbench
7 Release     : 07/10/2008 1.0
8 */
9 `timescale 1ns / 10ps
10 module mux_5_8_1_v_tb;
11
12 reg [ 4 : 0 ] a;
13 reg [ 4 : 0 ] b;
14 reg [ 4 : 0 ] c;
15 reg [ 4 : 0 ] d;
16 reg [ 4 : 0 ] e;
17 reg [ 4 : 0 ] f;
18 reg [ 4 : 0 ] g;
19 reg [ 4 : 0 ] h;
20 reg [ 2 : 0 ] sel;
21 wire [ 4 : 0 ] y;
22
23 mux_5_8_1_v2 u0 (
24 .a(a),
25 .b(b),
26 .c(c),
27 .d(d),
28 .e(e),
29 .f(f),
30 .g(g),
31 .h(h),
32 .sel(sel),
33 .y(y)
34 );
35
36 initial begin
37 a = 5 ' b0_0001;
38 b = 5 ' b0_0101;
39 c = 5 ' b0_0111;
40 d = 5 ' b0_1111;
41 e = 5 ' b0_1100;
42 f = 5 ' b0_0000;
43 g = 5 ' b0_1101;
44 h = 5 ' b0_0110;
45
46 sel = 3 ' b000;
47 end
48
49 always # 100 sel = sel + 1 ;
50
51 endmodule

mux01