simulink中利用HDL Coder生成Verilog代码时候,出现Native floating point code generation cannot generate :....
simulink中利用HDL Coder生成Verilog代码时候,出现Native floating point code generation cannot generate :…Signal rate of value inf found解决办法将提示错误的目标Block中constant模块的sample time 设置成实际采样率形式,不要设置成inf 或者 -1...