always@(posedge clk)时序赋值延迟一个周期
前几天是问了我一个小问题，我总结关键点如下：情形一：always@(posedge clk) begin if(ce == 1'b1 && ready == 1'b1) w_en <= 1'b1; else w_en <= 1'b0;end 情形二：always@(posedge clk) begin if(ce == 1'b1 &&a...
