HDL Count clock
1原题复现2.代码module top_module( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss); reg [3:0] ss_gewei=0; reg [3:0] ss_shiwei=0; reg [3:0] mm_gewei=0; reg [
