verilog 24进制+60进制 模拟时钟计数器
1、RTL代码module clock_24_60( clk, rst, hour_h, hour_l, minute_h, minute_l ); input clk,rst;output[3:0] hour_h,hour_l,minute_h,minute_l;reg[3:0] hour_h,hour_l,minute_h,minute_l;wire cout; //6
