Modelsim 报错 near “=“: syntax error, unexpected ‘=‘.
按照Verilog源程序写法如下：module shift; reg [3:0]start,result; initial; begin; start = 1; result = (start<<2); endendmoduleTranscript 命令行中用vlog 指令进行编译，显示如下错误参考文章：verilog error:syntax error-Is there a m
