python只使用位操作符和加号实现乘法、除法操作

def mul_cell(mult1, mult2, mult_acci):
if(mult2 & 0x01):
return [mult1 << 1, mult2 >> 1, mult_acci + mult1]
else:
return [mult1 << 1, mult2 >> 1, mult_acci]
def mult_man(mult1, mult2):
if mult2 > mult1:
mult1, mult2 = mult2, mult1
mult_acci = 0
while mult2 > 0:
mult1,mult2,mult_acci = mul_cell(mult1,mult2,mult_acci)
print(mult_acci)
mult_man(255,12)

根据verilog的流水级乘法器的原理

def divider_cell(divisor, dividend):
num_dividend = int('0b' + dividend, 2)
num_divisor = int('0b' + divisor, 2)
if num_divisor >= num_dividend:
return ['1', str(bin(num_divisor - num_dividend))[2:]]
else:
return ['0', str(bin(num_divisor))[2:]]
def get_binary_width(num):
res = 1
while (num >> 1) > 0:
res += 1;
num = num >> 1
return res
def divider_man(dividend, divisor):
merchant = ''
remainder = ''
dividend_width = get_binary_width(dividend)
divisor_width = get_binary_width(divisor)
return_info = divider_cell(str(bin(dividend))[2:divisor_width+2], str(bin(divisor))[2:])
merchant += return_info[0]
remainder = return_info[1]
for i in range(dividend_width - divisor_width):
return_info = divider_cell(remainder + str(bin(dividend))[2+divisor_width + i], str(bin(divisor))[2:])
merchant += return_info[0]
remainder = return_info[1]
print(int('0b' + merchant, 2))
print(int('0b' + remainder, 2))
divider_man(10,3)

根据verilog的流水线的触发器设计

最后

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