Vivado 常见报错

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我是靠谱客的博主大意金毛，最近开发中收集的这篇文章主要介绍Vivado 常见报错，觉得挺不错的，现在分享给大家，希望可以做个参考。

概述

1、[Synth 8-2543] port connections cannot be mixed ordered and named

说明例化时最后一个信号添加了一个逗号。

2、

原因：报告说明有一个管脚没有进行分配。

3、

从文件列表中发现

当一些文件的路径改变后，原来文件路径因为找不到文件的就会报红，新的文件不会自动替换原来的文件，这一点一定要注意，一定要手动删除。

4、

把约束文件.xdc内关于DEGUG core的信息全部删除后保存，再运行软件，弹出的界面话询问是save,还是load.

5、

在运行程序的时候点击，就会停止运行，所以一般不要点。

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u5_adc_module/adc1_in_clk_in] >

u5_adc_module/u1_IBUFGDS_inst (IBUFDS.O) is locked to IOB_X1Y146 and u5_adc_module/u1_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

该问题的解决办法：set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u5_adc_module/adc1_in_clk_in]

[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 5 out of 89 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led_alm, led_iso, led_agc, dn_pa_sw, up_pa_sw. 几个信号没有分配引脚

[IP_Flow 19-3805] Failed to generate and synthesize debug IP "xilinx.com:ip:xsdbm:1.0".

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).

ERROR: [Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: f:/Company_Prj/Date201509/xilinx_ics_100t/xilinx_wireless_ics_prj0915/xilinx_wireless_35t_prj0915/xilinx_wireless_35t_prj0915.runs/impl_1/.Xil/Vivado-12912-RD-PC/dbg_hub_CV.0/run/.srcs/sources_1/ip/dbg_hub_CV/fifo_generator_v12_0/hdl/fifo_generator_v12_0_vhsyn_rfs.vhd

[Chipscope 16-119] Implementing debug core dbg_hub failed.

ERROR: Could not generate core for dbg_hub. Aborting IP Generation operation.

ERROR: [Chipscope 16-218] An error occurred while trying to create or get a cached instance from the IP cache manager:

"IP generation failed see log file in f:/Company_Prj/Date201509/xilinx_ics_100t/xilinx_wireless_ics_prj0915/xilinx_wireless_35t_prj0915/xilinx_wireless_35t_prj0915.runs/impl_1/.Xil/Vivado-12912-RD-PC/dbg_hub_CV.0/out

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).

解决问题的办法：由于文件路径太长。把文件路径改短

=======================================================================================================

# ** Error: ./../../../H27V0-1SC-V02.srcs/sources_1/ip/coe_fifo/fifo_generator_v12_0/hdl/fifo_generator_v12_0.vhd(46)): in protected region.

对于这样的问题目前只能重建工程了

这种情况说明抓数据的文件和当前开发板中的文件是不对应的，应该重新烧写程序

转载于:https://www.cnblogs.com/zhongguo135/p/5916806.html