概述
文章目录
- 1. Four-bit binary counter
- 2. Decade counter
- 3. Decade counter again
- 4. Slow decade counter
- 5. Counter 1-12
- 6. Counter 1000
- 7. 4-digit decimal counter
- 8. 12-hour clock
1. Four-bit binary counter
构建一个从0到15的4位二进制计数器，周期为16。同步复位，复位应该将计数器重置为0。
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk)begin
if(reset)begin
q <= 4'b0;
end
else begin
q <= q+1'b1;
end
end
endmodule
2. Decade counter
构建一个从0到9(包括9)的十进制计数器，其周期为10。同步复位，复位应该将计数器重置为0。
module top_module(
input clk,
input reset,
output [3:0] q);
always@(posedge clk)begin
if(reset)begin
q <= 4'b0;
end
else if( q <= 4'b1000)begin
q <= q+1'b1;
end
else begin
q <= 4'b0;
end
end
endmodule
3. Decade counter again
制作一个从1到10的10进制计数器。同步复位，复位应该将计数器复位为1。
module top_module(
input clk,
input reset,
output [3:0] q);
always@(posedge clk)begin
if(reset)begin
q <= 4'b0001;
end
else if(q <= 4'b1001)begin
q <= q+1'b1;
end
else begin
q <= 4'b0001;
end
end
endmodule
4. Slow decade counter
构建一个从0到9(包括9)的十进制计数器，其周期为10。同步复位，复位应该将计数器重置为0。我们希望能够暂停计数器，而不是总是在每个时钟周期中递增，因此slowena输入指示计数器应该何时递增。
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk)begin
if(reset)begin
q <= 4'b0;
end
else if(slowena)begin
if(q <= 4'b1000)begin
q <= q+1'b1;
end
else begin
q <= 4'b0;
end
end
end
endmodule
5. Counter 1-12
设计一个1-12计数器
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = reset | ((Q == 4'd12)&&(enable == 1'b1));
assign c_d = c_load ? 4'd1 : 4'd0;
count4 the_counter (clk, c_enable, c_load, c_d ,Q );
endmodule
6. Counter 1000
例化BCD模块实现降频操作，1kHz->1Hz
module top_module(
input clk,
input reset,
output OneHertz,
output [2:0] c_enable);
wire [3:0] q0,q1,q2;
assign c_enable = {q1 == 4'd9 && q0 == 4'd9, q0 == 4'd9, 1'b1};
assign OneHertz = {q2 == 4'd9 && q1 == 4'd9 && q0 == 4'd9};
bcdcount counter0 (clk,reset,c_enable[0],q0);
bcdcount counter1 (clk,reset,c_enable[1],q1);
bcdcount counter2 (clk,reset,c_enable[2],q2);
endmodule
7. 4-digit decimal counter
设计一个4位BCD（二进制编码十进制）计数器。每个十进制数字使用4-bit来表示：q[3:0]是个位，q[7:4]是十位等。对于ena[3:1]，该信号用来表示个位、十位和百位的进位。时序图如下图所示:
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
count Inst1(.clk(clk), .reset(reset), .ena(1'b1), .q(q[3:0]));
count Inst2(.clk(clk), .reset(reset), .ena(q[3:0] == 4'd9), .q(q[7:4]));
count Inst3(.clk(clk), .reset(reset), .ena(q[7:4] == 4'd9 && q[3:0] == 4'd9), .q(q[11:8]));
count Inst4(.clk(clk), .reset(reset), .ena(q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9 ), .q(q[15:12]));
assign ena = {q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9,q[7:4] == 4'd9 && q[3:0] == 4'd9,q[3:0] == 4'd9};
endmodule
module count
(
input clk,
input reset,
input ena,
output reg[3:0] q
);
always @ (posedge clk)begin
if(reset)
q <= 4'b0;
else if (ena)begin
if(q <= 4'd1000)
q <= q+1'd1;
else
q <= 4'd0;
end
end
endmodule
8. 12-hour clock
用计数器设计一个带am/pm的12小时时钟。该计数器通过一个CLK进行计时，用ena使能信号来驱动时钟的递增。
reset信号将时钟复位为12：00 AM。 信号pm为0代表AM，为1代表PM。hh、mm和ss由两个BCD计数器构成hours(01~12)， minutes(00~59) , second(00~59)。Reset信号比enable信号有更高的优先级，即使没有enable信号也可以进行复位操作。
下图所示的时序图给出了从11:59:59 AM 到12 :00 : 00 PM的变化。
module top_module
(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
reg p; //0 is am, 1 is pm
reg [7:0] h;
reg [7:0] m;
reg [7:0] s;
always @ (posedge clk)
begin
if(reset) //reset to 12:00:00 AM
begin
p <= 0;
h <= 8'h12;
m <= 8'h00;
s <= 8'h00;
end
else
begin
if(ena)
begin
if(s < 8'h59)
begin
if(s[3:0] < 4'h9) //s[3:0] is ones digit
begin
s[3:0] <= s[3:0] + 1'h1;
end
else
begin
s[3:0] <= 0; //59->00
s[7:4] <= s[7:4] + 1'h1; //tens digit
end
end
else
begin
s <= 0; //s清零
if(m < 8'h59) //m同理s
begin
if(m[3:0] < 4'h9)
begin
m[3:0] <= m[3:0] + 1'h1;
end
else
begin
m[3:0] <= 0;
m[7:4] <= m[7:4] + 1'h1;
end
end
else
begin
m <= 1'h0;
if(h == 8'h11) //AM / PM 转换
p = !p;
if(h < 8'h12)
begin
if(h[3:0] < 4'h9)
h[3:0] <= h[3:0] + 1'h1;
else
begin
h[3:0] <= 4'h0;
h[7:4] <= h[7:4] + 1'h1;
end
end
else
begin //hour 12 -> 1
h <= 1'h1;
end
end
end
end
end
end
assign pm = p;
assign hh = h;
assign mm = m;
assign ss = s;
endmodule
最后
以上就是哭泣帅哥为你收集整理的HDLBits答案12-Counters1. Four-bit binary counter2. Decade counter3. Decade counter again4. Slow decade counter5. Counter 1-126. Counter 10007. 4-digit decimal counter8. 12-hour clock的全部内容，希望文章能够帮你解决HDLBits答案12-Counters1. Four-bit binary counter2. Decade counter3. Decade counter again4. Slow decade counter5. Counter 1-126. Counter 10007. 4-digit decimal counter8. 12-hour clock所遇到的程序开发问题。
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