HDLBits刷题（电路-移位寄存器）

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module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always @(posedge clk or posedge areset)begin
        if(areset) q<=4'd0;
        else if(load) q<=data;
        else if(ena) q<={1'b0,q[3:1]};
        else q<= q;
    end
endmodule

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module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    always @(posedge clk )begin
        if(load) q<=data;
        else if(ena==2'b01 ) q<={q[0],q[99:1]};
        else if(ena==2'b10 ) q<={q[98:0],q[99]};
        else q<=q;
    end
endmodule

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module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg signed[63:0] q); 
    always @(posedge clk )begin
        if(load) q<=data;
        else if(ena==1'b1&&amount==2'b01) q<=(q<<<8);
        else if(amount==2'b11 && ena==1'b1) q<=(q>>>8);
        else if(amount==2'b10 && ena==1'b1) q<=(q>>>1);
        else if(amount==2'b00 && ena==1'b1) q<=(q<<<1);
        else q<=q;
    end
endmodule

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module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output reg [4:0] q
); 
    always@(posedge clk)begin
        if (reset) q<=5'h1;
        else begin
            q[4]<=q[0]^1'b0;
            q[3]<=q[4];
            q[2]<=q[3]^q[0];
            q[1]<=q[2];
            q[0]<=q[1];
        end
    end
endmodule

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module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output reg [2:0] LEDR);  // Q
    always@(posedge KEY[0])begin
        LEDR[0]<=(KEY[1]?SW[0]:LEDR[2]);
        LEDR[1]<=(KEY[1]?SW[1]:LEDR[0]);
        LEDR[2]<=(KEY[1]?SW[2]:LEDR[1]^LEDR[2]);   
    end
endmodule

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module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output reg [31:0] q
); 
    integer i;
    always@(posedge clk)begin
        if (reset) q<=32'h1;
        else begin
            for(i=0;i<32;i=i+1'b1)begin
                if(i==31) q[i]<=q[0]^1'b0;
                else if((i==21)||(i==1)||(i==0)) q[i]<=q[i+1]^q[0];
                else q[i]<=q[i+1];
            end
        end
    end
endmodule

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module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    reg q1,q2,q3;
    always@(posedge clk)begin
        if (!resetn)  begin
            q3<=1'b0;
            q2<=1'b0;
            q1<=1'b0;
            out<=1'b0;
        end
        else begin
 			q3<=q2;
            q2<=q1;
            q1<=in;
            out<=q3;
        end
    end
endmodule

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module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); 
    MUXDFF m1(.W(LEDR[1]),.E(KEY[1]),.R(SW[0]),.L(KEY[2]),.CLK(KEY[0]),.Q(LEDR[0]));
    MUXDFF m2(.W(LEDR[2]),.E(KEY[1]),.R(SW[1]),.L(KEY[2]),.CLK(KEY[0]),.Q(LEDR[1]));
    MUXDFF m3(.W(LEDR[3]),.E(KEY[1]),.R(SW[2]),.L(KEY[2]),.CLK(KEY[0]),.Q(LEDR[2]));
    MUXDFF m4(.W(KEY[3]),.E(KEY[1]),.R(SW[3]),.L(KEY[2]),.CLK(KEY[0]),.Q(LEDR[3]));
endmodule

module MUXDFF (input W,input E,input R,input L,input CLK,output Q);
    always@(posedge CLK)begin
        Q<=L?R:(E?W:Q);
    end
endmodule

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module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    reg[7:0]q;
    always@(posedge clk)begin
        if(enable)begin
            q[0]<=S;
            q[1]<=q[0];
            q[2]<=q[1];
            q[3]<=q[2];
            q[4]<=q[3];
            q[5]<=q[4];
            q[6]<=q[5];
            q[7]<=q[6];
        end
        else
            q<=q;
    end
    assign Z=q[{A,B,C}];
endmodule